Lightweight Fault Detection Architecture for NTT on FPGA

2025-08-05

AI Summary

To address side-channel information leakage in post-quantum cryptography (PQC) Number Theoretic Transform (NTT) modules on FPGAs—caused by natural or adversarial fault injection—this paper proposes REMO, a lightweight fault-tolerant architecture. REMO integrates Montgomery-reduction-based recomputation with modular offset (Recomputation with Modular Offset) for butterfly-unit logic and memory rule checkers for NTT storage units, enabling real-time fault detection in both computational and memory subsystems. It supports mainstream PQC schemes including Kyber and NTRU, and is adaptable to multiple word lengths and fault models. Implemented on an Artix-7 FPGA, REMO consumes only 16 slices and one DSP, with a power dissipation of 3 mW. Fault detection coverage reaches 87.2%–100% for butterfly units and 50.7%–100% for memory regions. The design significantly improves both reliability and energy efficiency compared to prior approaches.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Natural Language Processing: Safety and Robustness

Application Category

• Security and Privacy: Applications of cryptography
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Systems and Infrastructure for Web, Mobile and WoT: Federated Web and WoT systems, including distributed, federated and edge-based data processing

Abstract

Post-Quantum Cryptographic (PQC) algorithms are mathematically secure and resistant to quantum attacks but can still leak sensitive information in hardware implementations due to natural faults or intentional fault injections. The intent fault injection in side-channel attacks reduces the reliability of crypto implementation in future generation network security procesors. In this regard, this research proposes a lightweight, efficient, recomputation-based fault detection module implemented on a Field Programmable Gate Array (FPGA) for Number Theoretic Transform (NTT). The NTT is primarily composed of memory units and the Cooley-Tukey Butterfly Unit (CT-BU), a critical and computationally intensive hardware component essential for polynomial multiplication. NTT and polynomial multiplication are fundamental building blocks in many PQC algorithms, including Kyber, NTRU, Ring-LWE, and others. In this paper, we present a fault detection method called : Recomputation with a Modular Offset (REMO) for the logic blocks of the CT-BU using Montgomery Reduction and another method called Memory Rule Checkers for the memory components used within the NTT. The proposed fault detection framework sets a new benchmark by achieving high efficiency with significant low implementation cost. It occupies only 16 slices and a single DSP block, with a power consumption of just 3mW in Artix-7 FPGA. The REMO-based detection mechanism achieves a fault coverage of 87.2% to 100%, adaptable across various word sizes, fault bit counts, and fault injection modes. Similarly, the Memory Rule Checkers demonstrate robust performance, achieving 50.7% to 100% fault detection depending on and the nature of injected faults.

Problem

• Detects faults in FPGA-based NTT for PQC security
• Addresses fault injection risks in cryptographic hardware
• Ensures reliable polynomial multiplication in PQC algorithms

Innovation

• Lightweight FPGA fault detection for NTT
• Recomputation with Modular Offset (REMO) method
• Memory Rule Checkers for NTT components