Mitigating Classical Resource Costs in Quantum Error Correction via Generalized qLDPC Predecoding

2026-05-04

AI Summary

This work addresses the severe classical resource contention in real-time decoding for fault-tolerant quantum computing with general qLDPC codes. We present the first automated, lightweight pre-decoder generation framework capable of supporting arbitrary qLDPC codes, overcoming the prior limitation to surface codes and substantially reducing manual design effort. The framework integrates an automated pre-decoding algorithm, an optimized ordered statistics decoding (OSD) procedure, and an efficient pipelined hardware architecture, enabling deployment on FPGAs or cryogenic ASICs. Experimental results demonstrate that the pre-decoder autonomously handles over 90% of decoding tasks, reducing the main decoder’s workload by up to 3,963× and cutting OSD computational cost by 72.71%. A single FPGA can support approximately 1,200 logical qubits for BB codes, while the cryogenic ASIC implementation scales to 36,000–360,000 logical qubits within a 1.5 W power budget.

Abstract

Quantum-classical interfaces (QCIs) for fault-tolerant quantum computing must manage simultaneous, real-time decoding across thousands to millions of logical qubits. Scaling these architectures necessitates sharing expensive decoding resources among logical qubits, which introduces severe resource contention within the QCI. While resolving these bottlenecks through efficient resource distribution remains a persistent challenge, lightweight predecoding holds promise to alleviate strain on shared decoding components by decreasing average latency and decoder usage. Notably, research into both decoder allocation and predecoding has been strictly confined to the surface code. With the growing emphasis on general quantum low-density parity-check (qLDPC) codes, slower decoding speeds will intensify resource contention, while the inherent complexity of these codes will render manual predecoder design unfeasible. To address this gap, we introduce an automated framework designed to generate predecoders for arbitrary qLDPC codes. These automatically constructed predecoders autonomously process over 90% of the decoding workload, cutting overall decoder utilization by up to 3,963x. This includes a reduction of up to 72.71% in computationally demanding ordered statistics decoding (OSD). Furthermore, we detail a highly efficient, pipelined hardware design that allows for the concurrent decoding of approximately 1,200 bivariate bicycle (BB) code logical qubits using a single FPGA. When implemented as a cryogenic ASIC, the architecture scales to support between 36,000 and 360,000 BB code logical qubits, operating within a 1.5 W power limit at 4 K.

Problem

• quantum error correction
• qLDPC codes
• quantum-classical interface
• resource contention
• predecoding

Innovation

• qLDPC codes
• predecoding
• automated framework
• resource contention
• cryogenic ASIC