High-throughput Low-latency Hardware Implementation of BCH Decoders

2026-06-16

AI Summary

This work addresses the challenge of achieving high-throughput, low-latency hardware implementations of BCH decoders that simultaneously support flexible error-correction capabilities and arbitrary code lengths. The authors propose two novel architectures: a conventional decoder based on the Berlekamp–Massey algorithm and Chien search, which accommodates any error-correction capability and code length, and a pioneering direct decoder that efficiently computes the roots of the error-locator polynomial, supporting up to t = 4 errors. Both architectures are optimized for Xilinx Ultrascale+ FPGAs and 16 nm FinFET technology. In 16 nm implementation, the (256,239) and (256,223) codes achieve single-cycle decoding with throughputs of 239 Gb/s and 223 Gb/s, respectively, and latencies of only 2–8 ns, substantially improving area efficiency and throughput performance.

Abstract

Two well-known decoding algorithms for BCH codes are conventional decoding, based on the Berlekamp-Massey algorithm in combination with Chien search, and direct decoding, which uses direct solutions to find the error locator polynomial and its roots. We introduce hardware architectures for conventional and direct decoding of extended BCH codes. Both architectures support implementation for any blocklength. Our conventional decoder supports any error-correction capability, whereas direct decoding is supported up to error correcting capability t = 4. To the best of our knowledge, our work is the first to implement a direct BCH decoder with an error-correction capability 4. We synthesize for the Xilinx Ultrascale+ XCZU48DR field-programmable gate-array and 16 nm FinFET for blocklengths up to 1024 bits and t = 4. We show that the direct decoder outperforms the conventional decoder in area efficiency for t = 2, t = 3, and for t = 4 for blocklengths longer than 256. Post-synthesis results for 16 nm FinFET show codeword per clock-cycle throughput at 1 GHz, achieving 239 Gb/s for the (256, 239) eBCH code and 223 Gb/s for (256, 223) eBCH code at 2 ns and 8 ns latency, respectively.

Problem

• BCH decoder
• high-throughput
• low-latency
• hardware implementation
• error-correction capability

Innovation

• BCH decoder
• direct decoding
• high-throughput
• low-latency
• hardware implementation