GSIM: Accelerating RTL Simulation for Large-Scale Designs

2025-08-04

AI Summary

RTL simulation is critical in hardware design, yet software-based simulation suffers from prohibitively low throughput for complex designs. This paper proposes a multi-level co-optimization methodology that systematically reduces four major computational overhead sources—across supernode, node, and bit-level abstractions—to build GSIM, an efficient open-source RTL simulator. Our approach innovatively integrates supernode-level scheduling, fine-grained event management, and bit-level computation optimization, while重构 the simulation engine via combined static analysis and runtime adaptive strategies. Experimental evaluation demonstrates that GSIM successfully simulates Linux boot on the XiangShan processor, achieving 7.34× speedup over Verilator; on the Rocket core, it attains 19.94× acceleration in CoreMark benchmarking. These results represent an order-of-magnitude performance improvement for large-scale RISC-V designs, establishing GSIM as a scalable, high-throughput RTL simulation framework.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Web Mining and Content Analysis: Web data generation and simulation
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Register Transfer Level (RTL) simulation is widely used in design space exploration, verification, debugging, and preliminary performance evaluation for hardware design. Among various RTL simulation approaches, software simulation is the most commonly used due to its flexibility, low cost, and ease of debugging. However, the slow simulation of complex designs has become the bottleneck in design flow. In this work, we explore the sources of computation overhead of RTL simulation and conclude them into four factors. To optimize these factors, we propose several techniques at the supernode level, node level, and bit level. Finally, we implement these techniques in a novel RTL simulator GSIM. GSIM succeeds in simulating XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, GSIM can achieve speedup of 7.34x for booting Linux on XiangShan, and 19.94x for running CoreMark on Rocket.

Problem

• Accelerating slow RTL simulation for complex hardware designs
• Reducing computation overhead in RTL simulation techniques
• Improving simulation speed for large-scale RISC-V processors

Innovation

• Optimizes RTL simulation at supernode level
• Enhances efficiency at node and bit levels
• Implements GSIM for significant speedup