Toward Intelligent Electronic-Photonic Design Automation for Large-Scale Photonic Integrated Circuits: from Device Inverse Design to Physical Layout Generation

2025-07-29

AI Summary

To address inefficiency, poor scalability, and error-proneness in large-scale photonic integrated circuit (PIC) design, this paper proposes PoLaRIS—an end-to-end electronic-photonic design automation framework. PoLaRIS integrates physics-driven optimization, machine learning, and domain-specific algorithms to enable, for the first time, co-optimization of fabrication-aware device inverse design and routing-aware placement. Its core components include a fabrication-aware inverse design engine, a routing-aware placement generator, a curvature-aware detailed router, and an ML-assisted performance optimization module. Experimental results demonstrate that PoLaRIS automatically generates DRC-compliant, performance-optimized full PIC layouts. At the thousand-device scale, it significantly improves design efficiency and scalability while drastically reducing manual intervention and error rates.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Intelligent Robots: Learning & Optimization for ROB

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

Photonic Integrated Circuits (PICs) offer tremendous advantages in bandwidth, parallelism, and energy efficiency, making them essential for emerging applications in artificial intelligence (AI), high-performance computing (HPC), sensing, and communications. However, the design of modern PICs, which now integrate hundreds to thousands of components, remains largely manual, resulting in inefficiency, poor scalability, and susceptibility to errors. To address these challenges, we propose PoLaRIS, a comprehensive Intelligent Electronic-Photonic Design Automation (EPDA) framework that spans both device-level synthesis and system-level physical layout. PoLaRIS combines a robust, fabrication-aware inverse design engine with a routing-informed placement and curvy-aware detailed router, enabling the automated generation of design rule violation (DRV)-free and performance-optimized layouts. By unifying physics-driven optimization with machine learning and domain-specific algorithms, PoLaRIS significantly accelerates PIC development, lowers design barriers, and lays the groundwork for scalable photonic system design automation.

Problem

• Automating large-scale photonic integrated circuit design
• Overcoming manual inefficiency in PIC component integration
• Ensuring DRV-free and performance-optimized layout generation

Innovation

• Fabrication-aware inverse design engine
• Routing-informed placement and curvy-aware router
• Physics-driven optimization with machine learning