ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems

2025-07-26

AI Summary

This work addresses the cost-optimization problem of chiplet partitioning in 2.5D heterogeneous integration. We propose a scalable, physically and process-aware partitioning methodology that innovatively integrates genetic algorithms—jointly optimizing chiplet decomposition and heterogeneous technology assignment—with simulated annealing for high-accuracy, I/O-constrained floorplanning. A fine-grained 2.5D packaging cost model is introduced, jointly accounting for interconnect bandwidth, transceiver reach constraints, and manufacturing feasibility. Evaluated on open-source benchmarks, our approach reduces total integration cost by up to 58% (geometric mean: 20%) over baseline methods, and by up to 47% (geometric mean: 6%) over Floorplet, significantly improving the performance-to-cost ratio of high-performance heterogeneous systems.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Machine Learning: Hardware-aware ML
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Industry adoption of chiplets has been increasing as a cost-effective option for making larger high-performance systems. Consequently, partitioning large systems into chiplets is increasingly important. In this work, we introduce ChipletPart - a cost-driven 2.5D system partitioner that addresses the unique constraints of chiplet systems, including complex objective functions, limited reach of inter-chiplet I/O transceivers, and the assignment of heterogeneous manufacturing technologies to different chiplets. ChipletPart integrates a sophisticated chiplet cost model with its underlying genetic algorithm-based technology assignment and partitioning methodology, along with a simulated annealing-based chiplet floorplanner. Our results show that: (i) ChipletPart reduces chiplet cost by up to 58% (20% geometric mean) compared to state-of-the-art min-cut partitioners, which often yield floorplan-infeasible solutions; (ii) ChipletPart generates partitions with up to 47% (6% geometric mean) lower cost as compared to the prior work Floorplet; and (iii) for the testcases we study, heterogeneous integration reduces cost by up to 43% (15% geometric mean) compared to homogeneous implementations. We also present case studies that show how changes in packaging or inter-chiplet signaling technologies can affect partitioning solutions. Finally, we make ChipletPart, the underlying chiplet cost model, and a chiplet testcase generator available as open-source tools for the community.

Problem

• Partitioning large systems into cost-effective chiplets
• Addressing constraints like I/O limits and heterogeneous technologies
• Optimizing chiplet cost and floorplan feasibility

Innovation

• Cost-driven 2.5D system partitioner
• Genetic algorithm-based technology assignment
• Simulated annealing-based chiplet floorplanner