Efficient Memristive Spiking Neural Networks Architecture with Supervised In-Situ STDP Method

2025-07-28

AI Summary

To address the demand for ultra-low-power, hardware-autonomous training, and scalable spiking neural network (SNN) architectures in battery-powered intelligent devices, this paper proposes a fully analog, memristor-native SNN architecture. The design intrinsically embeds lateral inhibition and refractory period mechanisms at the circuit level—eliminating the need for external microcontrollers—and introduces a supervised in-situ spike-timing-dependent plasticity (STDP) learning algorithm enabling full-synapse parallel updates under winner-take-all dynamics for hardware-autonomous training. Built upon memristor crossbar arrays and temporal coding, the architecture is validated via LTspice simulations: it achieves 99.11% and 97.9% classification accuracy on the Iris and Breast Cancer datasets, respectively; maintains a robust 93.4% average recognition rate under 20% input noise; and demonstrates excellent scalability with respect to both input dimensionality and output class count.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Memristor-based Spiking Neural Networks (SNNs) with temporal spike encoding enable ultra-low-energy computation, making them ideal for battery-powered intelligent devices. This paper presents a circuit-level memristive spiking neural network (SNN) architecture trained using a proposed novel supervised in-situ learning algorithm inspired by spike-timing-dependent plasticity (STDP). The proposed architecture efficiently implements lateral inhibition and the refractory period, eliminating the need for external microcontrollers or ancillary control hardware. All synapses of the winning neurons are updated in parallel, enhancing training efficiency. The modular design ensures scalability with respect to input data dimensions and output class count. The SNN is evaluated in LTspice for pattern recognition (using 5x3 binary images) and classification tasks using the Iris and Breast Cancer Wisconsin (BCW) datasets. During testing, the system achieved perfect pattern recognition and high classification accuracies of 99.11% (Iris) and 97.9% (BCW). Additionally, it has demonstrated robustness, maintaining an average recognition rate of 93.4% under 20% input noise. The impact of stuck-at-conductance faults and memristor device variations was also analyzed.

Problem

• Develops memristive SNN for ultra-low-energy computation
• Proposes supervised in-situ STDP learning algorithm
• Evaluates robustness in pattern recognition and classification

Innovation

• Memristor-based SNNs with supervised in-situ STDP
• Parallel synapse updates for efficient training
• Modular design for scalable input and output