DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling

2026-05-22

AI Summary

Traditional high-level synthesis (HLS) struggles to efficiently handle irregular memory accesses and large-scale datasets, limiting performance gains. This work proposes DAE4HLS, a decoupled access–execute (DAE) paradigm tailored for HLS that explicitly separates memory requests from responses, thereby unlocking memory-level parallelism that compilers cannot automatically exploit. The approach introduces an explicit decoupled programming model, reuses standard AXI Stream and AXI Burst interfaces, and integrates seamlessly into a dynamic HLS scheduling framework. Experimental results based on AMD Vitis HLS demonstrate that DAE4HLS achieves speedups of 10× to 79× across diverse irregular memory access patterns, substantially enhancing performance for non-uniform workloads.

Abstract

High-level synthesis (HLS) performs well for simple memory access patterns, such as for sequential accesses that can be turned into bursts, or for memory accesses into small datasets that can be stored in scratchpads. This limits HLS to accelerating only the low-hanging fruit, where memory-level parallelism is either trivially abundant, due to simple access patterns, or latency is low, due to the small dataset. Applications with more complex access patterns on large datasets would also benefit from acceleration, and would especially benefit from the reduction in design and verification effort that HLS promises. In this paper, we present DAE4HLS, a decoupled access-execute (DAE) paradigm for HLS. We propose a new programming model for explicitly decoupling requests and responses, which unlocks memory-level parallelism that otherwise cannot be automatically provided by a compiler. We apply the DAE4HLS paradigm to the commercial AMD Vitis HLS toolchain and show that the existing AXI stream and AXI burst interfaces can be repurposed for explicit decoupling. We further apply the paradigm to a dynamic-HLS framework, which is better suited for handling irregular workloads as compared to statically scheduled HLS. We show that support for explicit decoupling improves the performance and achieves a total speedup of 10-79$\times$.

Problem

• High-Level Synthesis
• Memory-Level Parallelism
• Complex Memory Access Patterns
• Large Datasets
• Decoupled Access-Execute

Innovation

• Decoupled Access-Execute
• High-Level Synthesis
• Memory-Level Parallelism
• Explicit Decoupling
• Dynamic HLS