🤖 AI Summary
To address the low spatial prediction accuracy, high computational overhead, and insufficient modeling of multi-source heterogeneous inputs in static IR-drop analysis for VLSI design, this paper proposes an attention-based U-Net framework incorporating weak-aware channel-wise gating. The method encodes metal-layer distributions, via patterns, and current-density maps as multi-channel physical layout inputs to formulate a pixel-wise regression task. A novel two-stage gated channel attention mechanism is introduced to dynamically enhance weakly responsive features while suppressing dominant channels, explicitly capturing channel heterogeneity. ConvNeXtV2 serves as the backbone for end-to-end joint modeling. Evaluated on the ICCAD-2023 benchmark, the proposed method achieves a 61.1% reduction in mean absolute error and a 71.0% improvement in F1 score, demonstrating significant gains in both prediction accuracy and robustness.
📝 Abstract
Accurate spatial prediction of power integrity issues, such as IR drop, is critical for reliable VLSI design. However, traditional simulation-based solvers are computationally expensive and difficult to scale. We address this challenge by reformulating IR drop estimation as a pixel-wise regression task on heterogeneous multi-channel physical maps derived from circuit layouts. Prior learning-based methods treat all input layers (e.g., metal, via, and current maps) equally, ignoring their varying importance to prediction accuracy. To tackle this, we propose a novel Weakness-Aware Channel Attention (WACA) mechanism, which recursively enhances weak feature channels while suppressing over-dominant ones through a two-stage gating strategy. Integrated into a ConvNeXtV2-based attention U-Net, our approach enables adaptive and balanced feature representation. On the public ICCAD-2023 benchmark, our method outperforms the ICCAD-2023 contest winner by reducing mean absolute error by 61.1% and improving F1-score by 71.0%. These results demonstrate that channel-wise heterogeneity is a key inductive bias in physical layout analysis for VLSI.