PRACtical: Subarray-Level Counter Update and Bank-Level Recovery Isolation for Efficient PRAC Rowhammer Mitigation

2025-07-24

AI Summary

DRAM density scaling exacerbates the Rowhammer effect. Although DDR5 introduces Proactive Refresh (PRAC) and Adaptive Bank Organization (ABO), PRAC’s bank-level precharge counting incurs latency, and its recovery refresh halts the entire memory channel, causing substantial performance overhead. This work proposes an efficient Rowhammer mitigation: a novel centralized subarray-level parallel counter circuit that refines PRAC’s update granularity from bank to subarray; combined with on-die register-based victim-bank identification, it enables fine-grained, bank-level recovery refresh—eliminating full-channel stalls. The design preserves strong Rowhammer resilience while delivering an average 8% system performance improvement (up to 20%), 19% energy reduction, and ≤6% performance impact under aggressive attack scenarios.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Search and Optimization: Distributed Search

Application Category

• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Security and Privacy: Large-scale security measurements

Abstract

As DRAM density increases, Rowhammer becomes more severe due to heightened charge leakage, reducing the number of activations needed to induce bit flips. The DDR5 standard addresses this threat with in-DRAM per-row activation counters (PRAC) and the Alert Back-Off (ABO) signal to trigger mitigation. However, PRAC adds performance overhead by incrementing counters during the precharge phase, and recovery refreshes stalls the entire memory channel, even if only one bank is under attack. We propose PRACtical, a performance-optimized approach to PRAC+ABO that maintains the same security guarantees. First, we reduce counter update latency by introducing a centralized increment circuit, enabling overlap between counter updates and subsequent row activations in other subarrays. Second, we enhance the $RFM_{ab}$ mitigation by enabling bank-level granularity: instead of stalling the entire channel, only affected banks are paused. This is achieved through a DRAM-resident register that identifies attacked banks. PRACtical improves performance by 8% on average (up to 20%) over the state-of-the-art, reduces energy by 19%, and limits performance degradation from aggressive performance attacks to less than 6%, all while preserving Rowhammer protection.

Problem

• Reduces PRAC counter update latency via centralized increment circuit
• Enables bank-level recovery isolation to avoid full channel stalls
• Maintains Rowhammer protection while improving performance and energy efficiency

Innovation

• Centralized increment circuit reduces counter update latency
• Bank-level recovery isolation pauses only affected banks
• DRAM-resident register identifies attacked banks efficiently