BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision

2026-07-04

AI Summary

This work addresses the challenge of efficient neural network inference for extended reality (XR) wearable devices under stringent ultra-low-power and latency constraints by proposing a hardware-software co-designed bit-serial CNN accelerator. The key innovation lies in a learnable, layer-wise bit-level early termination mechanism coupled with an adaptive bit-ordering strategy that dynamically exploits bit sparsity to eliminate redundant computations. Implemented in 12nm FinFET technology with voltage scaling (0.55–0.70 V), on-chip memory optimization, and dynamic bit processing, the accelerator occupies only 0.34 mm² and achieves an energy efficiency of 117.0 BTOPS/W (0.07 pJ per operation). It attains classification accuracies of 96.5% on DVS128 and 97.7% on N-MNIST, outperforming existing approaches by 4.0–22.1× in energy efficiency and up to 9.2% in accuracy.

Abstract

Extended Reality (XR) wearables require always-on perception within tight power envelopes of a few watts and motion-to-photon latency budgets below 20 ms, leaving only a few milliseconds for neural-network inference. Bit-serial computing is attractive for such energy-efficient neural network acceleration, but many existing architectures still process all bits even when ReLU sets the final output to zero. This paper presents BitFair, a software-hardware co-designed bit-serial CNN accelerator with learnable bit-level early termination and adaptive bit ordering, working under the ultra-low-power and strict latency requirements of XR applications. BitFair exploits dynamic bit-level sparsity by learning per-layer thresholds that trigger early termination when partial sums reliably predict that the final ReLU output will be zero. Furthermore, it searches for layer-wise bit orders that prioritize informative bits, maximizing early termination without sacrificing accuracy. A GlobalFoundries 12nm FinFET implementation with a core area of 0.34 mm^2, 104 KB on-chip memory, and voltage scaling from 0.55 to 0.70 V achieves sub-millisecond latency, up to 117.0 BTOPS/W, and 0.07 pJ/SOP. On IBM DVS128 Gesture and N-MNIST, BitFair achieves 96.5% and 97.7% accuracy, respectively, while improving effective energy efficiency by 4.0-22.1x and accuracy by up to 9.2% over prior fabricated XR vision accelerators.

Problem

• bit-serial computing
• early termination
• adaptive bit ordering
• ultra-low-power
• XR vision

Innovation

• bit-serial computing
• learnable early termination
• adaptive bit ordering
• ultra-low-power accelerator
• XR vision