SVAgent: AI Agent for Hardware Security Verification Assertion

2025-07-21

AI Summary

To address the low authoring efficiency and inadequate coverage of complex security vulnerabilities in SystemVerilog Assertions (SVA) for hardware security verification, this paper proposes SVAgent—the first automated SVA generation framework tailored for IC security verification. Its core innovation lies in a requirement decomposition mechanism that constructs fine-grained solving chains, integrated with an AI agent architecture, structured natural language understanding, and feedback-driven iterative refinement—effectively mitigating large language model hallucination and enhancing assertion accuracy and consistency. SVAgent is deeply integrated with formal verification interfaces, enabling seamless engineering-level interoperability with mainstream IC vulnerability assessment toolchains. Experiments demonstrate that SVAgent significantly outperforms existing approaches in assertion coverage, correctness, and generation efficiency. It has been successfully deployed in real-world chip projects, validating its industrial practicality and reliability.

Technology Category

• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Multiagent Systems: Adversarial Agents
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• Search and Retrieval-Augmented AI: Agentic search
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• Security and Privacy: Large-scale security measurements

Abstract

Verification using SystemVerilog assertions (SVA) is one of the most popular methods for detecting circuit design vulnerabilities. However, with the globalization of integrated circuit design and the continuous upgrading of security requirements, the SVA development model has exposed major limitations. It is not only inefficient in development, but also unable to effectively deal with the increasing number of security vulnerabilities in modern complex integrated circuits. In response to these challenges, this paper proposes an innovative SVA automatic generation framework SVAgent. SVAgent introduces a requirement decomposition mechanism to transform the original complex requirements into a structured, gradually solvable fine-grained problem-solving chain. Experiments have shown that SVAgent can effectively suppress the influence of hallucinations and random answers, and the key evaluation indicators such as the accuracy and consistency of the SVA are significantly better than existing frameworks. More importantly, we successfully integrated SVAgent into the most mainstream integrated circuit vulnerability assessment framework and verified its practicality and reliability in a real engineering design environment.

Problem

• Automate SystemVerilog assertion generation for security verification
• Address inefficiency in detecting modern circuit vulnerabilities
• Enhance accuracy and consistency in hardware security assessment

Innovation

• Automated SVA generation framework SVAgent
• Requirement decomposition for structured problem-solving
• Integration into mainstream vulnerability assessment frameworks