Enhancing Compiler Optimization Efficiency through Grammatical Decompositions of Control-Flow Graphs

2025-07-22

AI Summary

This work addresses key compiler optimization challenges—register allocation, speculative loop-oriented partial redundancy elimination (LOSPRE), and bank-selection-aware instruction placement—where conventional tree-decomposition-based approaches overlook the inherent sparsity of control-flow graphs (CFGs), resulting in excessive computational overhead. To overcome this, we propose SPL decomposition: the first CFG formalization framework leveraging Series-Parallel-Loop structural grammar to explicitly capture both sparsity and cyclic dependencies, modeled as a partially constrained satisfaction problem with a general-purpose solving methodology. Integrating enhanced tree decomposition and sparsity-aware instruction scheduling, our approach achieves significant reductions in computational cost across multiple benchmarks, while improving register allocation efficiency and data access latency.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Distributed Search

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Methods, algorithms and applications for the development of semantic models, knowledge graphs and other forms of structured data models with machine-interpretable semantics

Abstract

This thesis addresses the complexities of compiler optimizations, such as register allocation and Lifetime-optimal Speculative Partial Redundancy Elimination (LOSPRE), which are often handled using tree decomposition algorithms. However, these methods frequently overlook important sparsity aspects of Control Flow Graphs (CFGs) and result in high computational costs. We introduce the SPL (Series-Parallel-Loop) decomposition, a novel framework that offers optimal solutions to these challenges. A key contribution is the formulation of a general solution for Partial Constraint Satisfaction Problems (PCSPs) within graph structures, applied to three optimization problems. First, SPL decomposition enhances register allocation by accurately modeling variable interference graphs, leading to efficient register assignments and improved performance across benchmarks. Second, it optimizes LOSPRE by effectively identifying and eliminating redundancies in program execution. Finally, the thesis focuses on optimizing the placement of bank selection instructions to enhance data retrieval efficiency and reduce latency. Extensive experimentation demonstrates significant performance improvements over existing methods, establishing SPL decomposition as a powerful tool for complex compiler optimizations, including register allocation, LOSPRE, and bank selection.

Problem

• Improving compiler optimization efficiency using SPL decomposition
• Enhancing register allocation via accurate variable interference modeling
• Optimizing LOSPRE by eliminating redundancies in program execution

Innovation

• SPL decomposition optimizes register allocation efficiently
• SPL decomposition enhances LOSPRE by eliminating redundancies
• SPL decomposition improves bank selection instruction placement