🤖 AI Summary
Deploying the first layer of CNNs on resource-constrained embedded platforms (e.g., FPGAs, SoMs, SoCs, ASICs) faces challenges including high power consumption, limited real-time performance, and dependence on Python-based or HLS toolchains. To address these, this paper proposes smallNet—a compact, hand-coded Verilog convolutional layer architecture. smallNet employs fixed-point arithmetic and a filter-like polynomial structure, requiring no Xilinx IP cores, VLSI design tools, or external Python libraries, thereby enhancing hardware portability and deployment flexibility. Evaluated on a single-core Xilinx Zynq-7000 Cora Z7 platform, smallNet achieves 81.2% classification accuracy, delivers a 5.1× speedup over CPU-based inference, and consumes only 1.5 W total system power. This work establishes a lightweight, self-contained, and synthesizable hardware implementation paradigm for low-power, real-time edge intelligence.
📝 Abstract
Since current neural network development systems in Xilinx and VLSI require codevelopment with Python libraries, the first stage of a convolutional network has been implemented by developing a convolutional layer entirely in Verilog. This handcoded design, free of IP cores and based on a filter polynomial like structure, enables straightforward deployment not only on low cost FPGAs but also on SoMs, SoCs, and ASICs. We analyze the limitations of numerical representations and compare our implemented architecture, smallNet, with its computer based counterpart, demonstrating a 5.1x speedup, over 81% classification accuracy, and a total power consumption of just 1.5 W. The algorithm is validated on a single-core Cora Z7, demonstrating its feasibility for real time, resource-constrained embedded applications.