Emulated Integrity Replica: Enabling Self-Healing on FPGA SoCs via Hierarchical Twins

2026-07-13

AI Summary

This work addresses the challenges of deploying convolutional neural networks (CNNs) on FPGA-based SoCs in edge AI scenarios, where conventional fault-tolerance techniques often suffer from excessive redundancy overhead, high latency, or insufficient fault coverage. To overcome these limitations, the authors propose a hierarchical digital twin–based fault-tolerance framework that leverages idle cycles of the processing system to concurrently execute coarse-grained and fine-grained twin models, enabling efficient fault detection and precise recovery for accelerators implemented in programmable logic. The approach introduces a novel time-slack-driven, non-replicated fault-tolerance mechanism that integrates behavioral- and gate-level digital twins with periodic state capture and checkpoint-based recovery, achieving high detection speed and recovery accuracy without hardware redundancy. Experimental results demonstrate that, compared to dual modular redundancy (DMR), the proposed method significantly reduces area and energy overhead while attaining high fault coverage.

Abstract

Convolutional neural networks (CNNs) are increasingly being deployed on system-on-chip (SoC) platforms, where hardware-accelerated inference enables low-latency edge computing. Achieving fault tolerance on these devices remains challenging because conventional redundancy (dual/triple modular redundancy, DMR/TMR) incurs high resource cost, while software-centric methods (e.g., algorithm-based fault tolerance (ABFT), checkpoint-restart, instruction-level duplication, and software watchdogs/assertions) introduce nontrivial latency/energy overheads, reduce model accuracy, or provide inadequate coverage for accelerator-induced faults. In this paper, we propose Emulated Integrity Replica (EIR), a hierarchical digital-twin framework for FPGA SoCs that provides autonomous fault detection and recovery. Unlike DMR/TMR, which replicates hardware logic and incurs proportional area and power overheads, EIR avoids fabric-level duplication by exploiting temporal slack in the processing system (PS). During accelerator execution in the programmable logic (PL), the PS typically remains underutilized; EIR capitalizes on these idle cycles to host two complementary twins: (i) Rabbit: a coarse-grained behavioral model for rapid fault detection and (ii) Tortoise: a fine-grained gate-level model that performs precise recovery from checkpointed states. The accelerator state is captured periodically, leveraging the accelerator's execution-speed profiling to balance performance overhead and resilience. Experiments on representative workloads show that EIR achieves high empirical fault coverage relative to a DMR baseline while reducing energy and area under the evaluated fault model and workload assumptions, indicating a practical path to resilient edge-AI deployments under strict resource budgets.

Problem

• fault tolerance
• FPGA SoC
• convolutional neural networks
• hardware redundancy
• edge computing

Innovation

• Emulated Integrity Replica
• Hierarchical Digital Twin
• FPGA SoC
• Self-Healing
• Fault Tolerance