VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair

2025-07-21

AI Summary

This work addresses the underexplored problem of automatic RTL-level code repair for Design-for-Testability (DFT) in electronic design automation (EDA). Methodologically, it introduces the first Retrieval-Augmented Generation (RAG)-based LLM-assisted EDA framework tailored for DFT, featuring an autoencoder-based RTL structural similarity retrieval mechanism and an iterative, LLM-driven repair pipeline that jointly ensures DFT compliance and synthesis feasibility. Key contributions include: (1) establishing the DFT-RAG paradigm; (2) enabling end-to-end automated RTL repair; and (3) achieving a 7.72× improvement in repair success rate over zero-shot baselines. Ablation studies validate the effectiveness of each component. All code, datasets, and models are publicly released.

Technology Category

• Planning, Routing, and Scheduling: Replanning and Plan Repair
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Machine Learning: Deep Generative Models & Autoencoders

Application Category

• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Economics, Online Markets and Human Computation: LLM based quality controls for crowd work
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

Large language models (LLMs) have demonstrated immense potential in computer-aided design (CAD), particularly for automated debugging and verification within electronic design automation (EDA) tools. However, Design for Testability (DFT) remains a relatively underexplored area. This paper presents VeriRAG, the first LLM-assisted DFT-EDA framework. VeriRAG leverages a Retrieval-Augmented Generation (RAG) approach to enable LLM to revise code to ensure DFT compliance. VeriRAG integrates (1) an autoencoder-based similarity measurement model for precise retrieval of reference RTL designs for the LLM, and (2) an iterative code revision pipeline that allows the LLM to ensure DFT compliance while maintaining synthesizability. To support VeriRAG, we introduce VeriDFT, a Verilog-based DFT dataset curated for DFT-aware RTL repairs. VeriRAG retrieves structurally similar RTL designs from VeriDFT, each paired with a rigorously validated correction, as references for code repair. With VeriRAG and VeriDFT, we achieve fully automated DFT correction -- resulting in a 7.72-fold improvement in successful repair rate compared to the zero-shot baseline (Fig. 5 in Section V). Ablation studies further confirm the contribution of each component of the VeriRAG framework. We open-source our data, models, and scripts at https://github.com/yuyangdu01/LLM4DFT.

Problem

• Automated RTL testability repair using LLMs
• Retrieval-augmented generation for DFT compliance
• Improving DFT correction success rate significantly

Innovation

• LLM-assisted DFT-EDA framework using RAG
• Autoencoder-based RTL similarity measurement
• Iterative code revision for DFT compliance