EPAC: The Last Dance

2026-04-14

AI Summary

This work presents EPAC, a heterogeneous RISC-V accelerator chip designed and tape-out to support Europe’s strategic need for an autonomous high-performance computing (HPC) ecosystem. Fabricated in GlobalFoundries 22FDX FD-SOI technology, EPAC integrates three specialized compute units—Vector (VEC), Stencil/Machine Learning many-core (STX), and Variable-Precision Floating-Point (VRP)—interconnected via the CHI protocol with distributed L2 caches and equipped with high-speed SerDes interfaces. As the first fully functional RISC-V HPC accelerator developed in Europe, EPAC has successfully undergone multi-institutional tape-out and board-level boot-up, with all core IPs validated functionally. It uniquely unifies high-precision HPC, stencil, machine learning, and variable-precision computing paradigms within a single architecture, establishing a critical hardware foundation for a sovereign European HPC processor ecosystem.

Technology Category

• Machine Learning: Hardware-aware ML
• Humans and AI: Other Foundations of Human Computation & AI
• Philosophy and Ethics of AI: AI & Epistemology

Application Category

• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Security and Privacy: Privacy-enhancing technologies
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European HPC processor ecosystem. EPAC is implemented in GlobalFoundries 22FDX (GF22FDX) technology, covers an area of 27 sq mm with approximately 0.3 billion transistors, and integrates three distinct RISC-V compute tiles targeting different workload classes: VEC, a vector processing tile for double-precision HPC workloads; STX, a many-core tile optimized for stencil and machine learning computations; and VRP, a variable-precision tile for iterative numerical solvers requiring extended floating-point formats. All tiles are connected through a Coherent Hub Interface (CHI) based network-on-chip with a distributed L2 cache system and communicate with external memory via a SerDes link. The chip was taped out in GF22FDX technology and successfully brought up, with all major IP blocks validated. This paper describes the architecture of each tile and the uncore infrastructure, the integration and physical implementation process, and the board-level bring-up activities. It also reflects on the engineering and coordination lessons learned from a full chip design effort distributed across academic and industrial partners in Europe.

Problem

• RISC-V
• HPC accelerator
• European Processor Initiative
• heterogeneous computing
• chip design

Innovation

• RISC-V
• heterogeneous accelerator
• vector processing
• variable-precision computing
• Network-on-Chip