🤖 AI Summary
This work addresses the challenge that analog neural networks exhibit significant circuit-level deviations from their nominal models due to process variations, while existing verification methods suffer from poor efficiency. To overcome this, the paper introduces, for the first time, a polynomial modeling approach to capture the nonlinear behavior of neuron circuits under process variations and integrates it with polynomial zonotopes for reachability analysis, enabling efficient formal verification. The proposed method eliminates the need for time-consuming Monte Carlo simulations and demonstrates remarkable scalability: it successfully verifies fully connected and convolutional analog neural networks across three datasets, reducing verification time from days to seconds while covering 99% of variation samples, thereby substantially enhancing both the scalability and reliability of analog neural network verification.
📝 Abstract
Analog neural networks are gaining attention due to their efficiency in terms of power consumption and processing speed. However, since analog neural networks are implemented as physical circuits, they are highly sensitive to manufacturing process variations, which can cause large deviations from the nominal model. We present a polynomial-based model that resembles the performance of the neuron circuit under process variations. Then, we formally verify the behavior of the circuit-level model using reachability analysis with polynomial zonotopes, thus, avoiding conventional, time-consuming Monte Carlo simulations. We evaluate our proposed verification approach on three different datasets, verifying both fully-connected and convolutional analog neural networks. Our experimental results confirm the effectiveness of our verification approach by reducing the verification time from days to seconds while enclosing 99% of the variation samples.