High-Performance Pipelined NTT Accelerators with Homogeneous Digit-Serial Modulo Arithmetic

2025-07-16

AI Summary

Large-modulus Number-Theoretic Transforms (NTTs) in fully homomorphic encryption (FHE) suffer from severe frequency degradation and high area overhead in hardware implementations due to expensive high-bitwidth modular arithmetic. Method: This paper proposes a uniform pipelined architecture leveraging isomorphic digit-serial modular arithmetic and redundant modular representation. It integrates serial modular adders/multipliers, redundant data encoding, and deep pipelining while eliminating the conventional serial-to-parallel conversion bottleneck—enabling unified low-bitwidth processing. Contribution/Results: The design achieves co-optimization of high clock frequency and high parallelism on both FPGA and ASIC platforms. Experimental evaluation demonstrates significant resource reduction and markedly improved throughput over state-of-the-art (SOTA) approaches under comparable performance and memory bandwidth constraints.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Security and Privacy: Applications of cryptography
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Systems and Infrastructure for Web, Mobile and WoT: Federated Web and WoT systems, including distributed, federated and edge-based data processing

Abstract

The Number Theoretic Transform (NTT) is a fundamental operation in privacy-preserving technologies, particularly within fully homomorphic encryption (FHE). The efficiency of NTT computation directly impacts the overall performance of FHE, making hardware acceleration a critical technology that will enable realistic FHE applications. Custom accelerators, in FPGAs or ASICs, offer significant performance advantages due to their ability to exploit massive parallelism and specialized optimizations. However, the operation of NTT over large moduli requires large word-length modulo arithmetic that limits achievable clock frequencies in hardware and increases hardware area costs. To overcome such deficits, digit-serial arithmetic has been explored for modular multiplication and addition independently. The goal of this work is to leverage digit-serial modulo arithmetic combined with appropriate redundant data representation to design modular pipelined NTT accelerators that operate uniformly on arbitrary small digits, without the need for intermediate (de)serialization. The proposed architecture enables high clock frequencies through regular pipelining while maintaining parallelism. Experimental results demonstrate that the proposed approach outperforms state-of-the-art implementations and reduces hardware complexity under equal performance and input-output bandwidth constraints.

Problem

• Improving NTT efficiency for FHE acceleration
• Overcoming large moduli hardware limitations
• Enhancing clock frequency with digit-serial arithmetic

Innovation

• Homogeneous digit-serial modulo arithmetic for NTT
• Pipelined accelerators without intermediate (de)serialization
• Redundant data representation for high clock frequencies