Compute SNR-Optimal Analog-to-Digital Converters for Analog In-Memory Computing

2025-07-13

AI Summary

To address the overestimation of analog-to-digital converter (ADC) precision requirements in analog in-memory computing (AIMC), which unnecessarily constrains energy efficiency, this paper proposes a computation signal-to-noise ratio (CSNR)-driven ADC precision optimization framework. We introduce a circuit-aware CSNR analytical model that abandons the conventional assumption of input-independent, white quantization noise—enabling more accurate noise characterization. Based on this model, we develop the CACTUS algorithm to jointly optimize ADC bitwidth, gain, and reference voltage. Evaluated on a 28 nm SRAM-based behavioral-level AIMC platform for 256-dimensional binary dot-product computation, our approach reduces required ADC precision by three bits compared to conventional methods while improving CSNR by 6 dB. This yields significant ADC power reduction and enhanced computational accuracy, demonstrating a principled trade-off between precision, energy, and fidelity in AIMC systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Search and Optimization: Learning to Search

Application Category

• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs

Abstract

Analog in-memory computing (AIMC) is an energy-efficient alternative to digital architectures for accelerating machine learning and signal processing workloads. However, its energy efficiency is limited by the high energy cost of the column analog-to-digital converters (ADCs). Reducing the ADC precision is an effective approach to lowering its energy cost. However, doing so also reduces the AIMC's computational accuracy thereby making it critical to identify the minimum precision required to meet a target accuracy. Prior works overestimate the ADC precision requirements by modeling quantization error as input-independent noise, maximizing the signal-to-quantization-noise ratio (SQNR), and ignoring the discrete nature of ideal pre-ADC signal. We address these limitations by developing analytical expressions for estimating the compute signal-to-noise ratio (CSNR), a true metric of accuracy for AIMCs, and propose CACTUS, an algorithm to obtain CSNR-optimal ADC parameters. Using a circuit-aware behavioral model of an SRAM-based AIMC in a 28nm CMOS process, we show that for a 256-dimensional binary dot product, CACTUS reduces the ADC precision requirements by 3b while achieving 6dB higher CSNR over prior methods. We also delineate operating conditions under which our proposed CSNR-optimal ADCs outperform conventional SQNR-optimal ADCs.

Problem

• Optimize ADC precision for analog in-memory computing energy efficiency
• Develop CSNR metric to accurately assess AIMC computational accuracy
• Propose CACTUS algorithm to reduce ADC precision requirements

Innovation

• Develops CSNR metric for accuracy estimation
• Proposes CACTUS algorithm for optimal ADCs
• Reduces ADC precision by 3 bits