AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design

2025-07-14

AI Summary

In analog circuit design, testbench construction remains manual, severely hindering full-flow automation—particularly in reproducing published circuits, where it suffers from low efficiency and poor flexibility. This paper proposes the first end-to-end, large language model (LLM)-based framework for automatic testbench generation, integrating domain-specific knowledge injection, structured information extraction from research papers, simulation strategy reasoning, and Tsinghua Electronic Design (TED) code generation. We curate a specialized training dataset covering three canonical analog circuits: operational amplifiers, bandgap references, and low-dropout regulators. Experimental results demonstrate that our method generates high-accuracy, directly simulatable TED testbench code, significantly accelerating circuit reproduction. Moreover, it establishes a scalable framework and supplies high-quality, domain-enriched knowledge resources to advance automated EDA research.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Cognitive Modeling & Cognitive Systems: Analogy
• Natural Language Processing: Generation

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

Recent advancements have demonstrated the significant potential of large language models (LLMs) in analog circuit design. Nevertheless, testbench construction for analog circuits remains manual, creating a critical bottleneck in achieving fully automated design processes. Particularly when replicating circuit designs from academic papers, manual Testbench construction demands time-intensive implementation and frequent adjustments, which fails to address the dynamic diversity and flexibility requirements for automation. AnalogTester tackles automated analog design challenges through an LLM-powered pipeline: a) domain-knowledge integration, b) paper information extraction, c) simulation scheme synthesis, and d) testbench code generation with Tsinghua Electronic Design (TED). AnalogTester has demonstrated automated Testbench generation capabilities for three fundamental analog circuit types: operational amplifiers (op-amps), bandgap references (BGRs), and low-dropout regulators (LDOs), while maintaining a scalable framework for adaptation to broader circuit topologies. Furthermore, AnalogTester can generate circuit knowledge data and TED code corpus, establishing fundamental training datasets for LLM specialization in analog circuit design automation.

Problem

• Automates testbench generation for analog circuits using LLMs
• Reduces manual effort in replicating circuit designs from papers
• Supports diverse analog circuit types with scalable framework

Innovation

• LLM-powered pipeline for analog design
• Automated testbench generation for circuits
• Generates circuit knowledge and TED code