High-performance Vector-length Agnostic Quantum Circuit Simulations on ARM Processors

2026-02-10

AI Summary

This work proposes the first vector-length-agnostic (VLA) design paradigm for quantum state-vector simulation on ARM processors supporting variable vector lengths. By integrating VLEN-adaptive memory layouts, load buffering, fine-grained loop control, and gate fusion techniques, the approach enables a single source code to achieve high-performance, portable simulation across diverse ARM platforms. The study introduces a systematic evaluation framework combining PMU events with novel quantitative metrics to assess vectorization efficacy. Experimental results demonstrate speedups of up to 4.5×, 2.5×, and 1.5× on the A64FX, Grace, and Graviton3 processors, respectively, confirming both the high performance and cross-platform portability of the proposed methodology.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Computer Vision: Learning & Optimization for CV

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Security and Privacy: Large-scale security measurements

Abstract

ARM SVE and RISC-V RVV are emerging vector architectures in high-end processors that support vectorization of flexible vector length. In this work, we leverage an important workload for quantum computing, quantum state-vector simulations, to understand whether high-performance portability can be achieved in a vector-length agnostic (VLA) design. We propose a VLA design and optimization techniques critical for achieving high performance, including VLEN-adaptive memory layout adjustment, load buffering, fine-grained loop control, and gate fusion-based arithmetic intensity adaptation. We provide an implementation in Google's Qsim and evaluate five quantum circuits of up to 36 qubits on three ARM processors, including NVIDIA Grace, AWS Graviton3, and Fujitsu A64FX. By defining new metrics and PMU events to quantify vectorization activities, we draw generic insights for future VLA designs. Our single-source implementation of VLA quantum simulations achieves up to 4.5x speedup on A64FX, 2.5x speedup on Grace, and 1.5x speedup on Graviton.

Problem

• Vector-length Agnostic
• Quantum Circuit Simulation
• ARM SVE
• Performance Portability
• Quantum State-vector

Innovation

• Vector-Length Agnostic
• Quantum Circuit Simulation
• ARM SVE
• Gate Fusion
• Memory Layout Optimization