Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads

2025-07-07

AI Summary

Prior simulation-based studies overestimate the performance overhead of Per-Row Activation Counting (PRAC), a DRAM read-disturb mitigation mechanism, due to unrealistic modeling of timing impacts. Method: We conduct the first systematic evaluation of PRAC on real hardware, using microbenchmarks and SPEC CPU2017 workloads to quantify its actual performance impact and investigate latency-hiding via page-closing policies. Contribution/Results: PRAC incurs only 1.06% average and 3.28% maximum performance overhead—up to 9.15× lower than simulator predictions. This corrects longstanding misconceptions about PRAC’s cost. Our study fills a critical gap in empirical hardware validation of PRAC and demonstrates its practical feasibility on modern CPU platforms, providing essential evidence for deploying DRAM reliability mechanisms in production systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Reasoning under Uncertainty: Stochastic Optimization
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.

Problem

• Measure real hardware performance of PRAC method
• Compare PRAC overheads between simulators and real CPUs
• Analyze impact of close page policy on PRAC overheads

Innovation

• First real-machine PRAC performance analysis
• PRAC modifies DRAM timing parameters
• Close page policy minimizes overhead