Voltage Mode Winner-Take-All Circuit for Neuromorphic Systems

2025-07-06

AI Summary

To address the demand for low-power, high-throughput winner-takes-all (WTA) circuits enabling on-chip learning in neuromorphic systems, this work proposes a configurable voltage-mode WTA circuit supporting k-winners selection and tunable hysteresis to enhance stability under dynamic inputs and adaptability across diverse tasks. Implemented in IBM 65 nm CMOS technology, the design operates entirely in the voltage domain to optimize the power–delay trade-off. Post-layout simulations demonstrate an ultra-low power consumption of 34.9 μW and a rapid response latency of 10.4 ns for 1,000-input configurations—significantly outperforming state-of-the-art current-mode counterparts. The circuit’s configurability enables flexible deployment in edge-intelligence applications such as spatial filtering and real-time classification. By unifying energy efficiency, speed, and functional adaptability, this work provides a novel architectural foundation for efficient brain-inspired learning hardware.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Computer Vision: Learning & Optimization for CV

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Recent advances in neuromorphic computing demonstrate on-device learning capabilities with low power consumption. One of the key learning units in these systems is the winner-take-all circuit. In this research, we propose a winner-take-all circuit that can be configured to achieve k-winner and hysteresis properties, simulated in IBM 65 nm node. The circuit dissipated 34.9 $μ$W of power with a latency of 10.4 ns, while processing 1000 inputs. The utility of the circuit is demonstrated for spatial filtering and classification.

Problem

• Designing a configurable winner-take-all circuit for neuromorphic systems
• Achieving low power consumption and high speed processing
• Demonstrating utility in spatial filtering and classification tasks

Innovation

• Voltage Mode Winner-Take-All Circuit
• Configurable k-winner and hysteresis properties
• Low power 34.9 μW with 10.4 ns latency