🤖 AI Summary
To address the bottlenecks of conventional true random number generators (TRNGs) in cryptographic systems—including low throughput, high area and power overhead, and reliance on post-processing—this paper proposes a root-of-trust-oriented, high-energy-efficiency TRNG architecture. The design innovatively integrates dynamic entropy source fusion, adaptive sampling control, and timing jitter enhancement circuits, enabling direct compliance with all NIST SP 800-22 and AIS-31 randomness tests without post-processing. Implemented on FPGA, it occupies only eight logic slices and achieves throughputs of 670 Mbps on Virtex-6 and 620 Mbps on Artix-7. Its throughput-per-slice-per-watt metric improves by 2.63× over prior art. Moreover, the architecture supports cross-process technology portability, significantly advancing the co-optimization frontier of speed, area, and power efficiency.
📝 Abstract
As a vital security primitive, the true random number generator (TRNG) is a mandatory component to build roots of trust for any encryption system. However, existing TRNGs suffer from bottlenecks of low throughput and high area-energy consumption. In this work, we propose DH-TRNG, a dynamic hybrid TRNG circuitry architecture with ultra-high throughput and area-energy efficiency. Our DH-TRNG exhibits portability to distinct process FPGAs and passes both NIST and AIS-31 tests without any post-processing. The experiments show it incurs only 8 slices with the highest throughput of 670Mbps and 620Mbps on Xilinx Virtex-6 and Artix-7, respectively. Compared to the state-of-the-art TRNGs, our proposed design has the highest Throughput/SlicesPower with a 2.63 times increase.