Machine Learning-Based Graph Simplification for Symbolic Accelerators

2026-05-09

AI Summary

This work proposes AutoSlim, a novel framework that introduces machine learning–driven graph simplification into symbolic accelerator design to address the high memory overhead and low execution efficiency caused by redundant graph structures. AutoSlim employs a random forest classifier to predict node importance, leveraging automaton graph features and historical execution data to perform data-driven pruning of nondeterministic finite automata. Functional equivalence is rigorously preserved through formal verification. Experimental evaluation on the NAPOLY+ architecture demonstrates that AutoSlim achieves up to 40% reduction in FPGA resource utilization while significantly improving throughput and energy efficiency, all without compromising behavioral correctness.

Abstract

Graph-based accelerators have been widely adopted in symbolic data processing applications such as genomics, cybersecurity, and artificial intelligence. However, these systems often suffer from excessive memory usage and inefficiencies stemming from redundant graph structures. We present AutoSlim, a machine learning-based framework that leverages data-driven methods to prune automata graphs for hardware accelerators. Using features extracted from prior graph executions and a Random Forest classifier, AutoSlim identifies and removes low-impact nodes and edges. When applied to a Non-deterministic Finite Automata overlay architecture (NAPOLY+), AutoSlim reduces FPGA resource usage by up to 40%, with corresponding improvements in throughput and power efficiency. The framework includes a verification step to ensure functional equivalence after pruning and suggests promising directions for both hardware optimization and security.

Problem

• graph simplification
• symbolic accelerators
• memory efficiency
• redundant graph structures
• hardware acceleration

Innovation

• graph simplification
• machine learning
• symbolic accelerators
• automata pruning
• FPGA optimization