Low-Complexity Beamspace Channel Denoiser for mmWave Massive MIMO with Low-Resolution ADCs

2026-05-09

AI Summary

This work addresses the challenge of channel estimation in millimeter-wave massive MIMO systems with low-resolution analog-to-digital converters (ADCs), where performance is degraded by the combined effects of thermal and quantization noise. Exploiting the sparsity of channels in the beam domain, the authors formulate denoising as a Bayesian binary hypothesis test and derive a closed-form threshold using a Bernoulli–complex Gaussian prior. A hard-thresholding rule is then applied to separate signal components from noise. The proposed algorithm achieves near-linear computational complexity, circumventing matrix inversion and iterative optimization. Furthermore, a hardware-aware VLSI architecture is designed to support sublinear scaling with respect to the number of antennas. FPGA implementation on an AMD-Xilinx KCU116 platform demonstrates that the approach significantly reduces latency and hardware resource consumption while achieving performance comparable to high-complexity methods.

Abstract

In this paper, we propose a low-complexity beamspace channel denoising algorithm for millimeter-wave (mmWave) massive multi-input multi-output (MIMO) systems with low-resolution analog-to-digital converters (ADCs). The proposed method exploits the inherent sparsity of mmWave channels in the beamspace domain and formulates the denoising problem as a Bayesian binary hypothesis testing under a Bernoulli-complex Gaussian prior. To capture the distortion induced by low-resolution ADCs in a complexity-efficient manner, thermal noise and quantization noise are jointly modeled as a composite noise. Based on this modeling, a closed-form threshold value and a hard-thresholding-based denoising rule are derived to distinguish signal-dominant and noise-dominant components. The resulting algorithm avoids computationally intensive operations such as matrix inversion, iterative optimization, and parameter searching, and achieves near-linear computational complexity with respect to the number of antennas. Furthermore, a hardware-efficient very large-scale integration (VLSI) architecture is developed to enable practical deployment of the proposed algorithm, and is implemented on an AMD-Xilinx Kintex UltraScale+ KCU116 FPGA platform. The design incorporates hardware-aware simplifications and an efficient processing structure, leading to significantly lower latency and reduced hardware resource utilization compared to existing hardware implementations, along with sublinear scaling as the number of antennas increases. Extensive simulation results demonstrate that the proposed method achieves performance comparable to computationally intensive existing approaches while significantly reducing computational complexity.

Problem

• mmWave
• massive MIMO
• low-resolution ADCs
• beamspace channel denoising
• computational complexity

Innovation

• beamspace channel denoising
• low-resolution ADCs
• Bayesian hypothesis testing
• composite noise modeling
• hardware-efficient VLSI