AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding

2026-02-10

AI Summary

Existing sequence-based methods for analog circuit topology generation rely heavily on expert knowledge and suffer from low electrical validity and a tendency to overfit training samples. This work proposes AnalogToBi, a novel framework that represents circuits using bipartite graph structures and integrates circuit-type conditioning, device renaming for data augmentation, and a context-free grammar–guided decoding mechanism. Without requiring manual intervention or human-in-the-loop training, AnalogToBi significantly enhances both the electrical validity and novelty of generated topologies while effectively mitigating memorization of training examples.

Abstract

Analog circuit design remains highly dependent on expert knowledge due to the complexity of device-level interactions and topology design. Recent transformer-based approaches for device-level topology generation have shown promise, yet they suffer from low electrical validity without human-in-the-loop (HITL) training and severe memorization caused by sequence-based circuit representations. In this work, we propose AnalogToBi, a framework for device-level analog circuit topology generation. AnalogToBi introduces circuit-type conditioning for categorizing heterogeneous multi-type topology datasets, device renaming augmentation to mitigate memorization, a bipartite graph representation for improved structural generalization, and grammar-guided decoding to enforce structural validity during bipartite graph generation. Experimental results demonstrate that AnalogToBi achieves high validity and novelty without HITL training while effectively avoiding memorization of training topologies. Our code is available at https://github.com/Seungmin0825/AnalogToBi.

Problem

• analog circuit design
• topology generation
• device-level
• electrical validity
• memorization

Innovation

• bipartite graph
• grammar-guided decoding
• device-level topology generation
• circuit-type conditioning
• device renaming augmentation