Stateful Logic In-Memory Using Gain-Cell eDRAM

2025-06-29

AI Summary

To address the memory wall and energy-efficiency bottlenecks in data-intensive applications, this work proposes an in-memory computing (IMC) architecture based on gain-cell embedded DRAM (GC-eDRAM). Unlike conventional SRAM or eDRAM, our approach uniquely exploits GC-eDRAM’s dual-port capability and non-destructive read mechanism to perform stateful logic operations directly within the memory array, thereby drastically reducing data movement. We introduce a customized processing-in-memory (PIM) circuit design that ensures high-reliability in-memory logic execution. Circuit-level simulations demonstrate a logic operation success rate of 99.5%, a data retention time of 5 μs, and significant improvements in both energy efficiency and computational density over baseline architectures. This work establishes a scalable hardware foundation for high-density, low-power compute-in-memory chips.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Modern data-intensive applications demand memory solutions that deliver high-density, low-power, and integrated computational capabilities to reduce data movement overhead. This paper presents the use of Gain-Cell embedded DRAM (GC-eDRAM) - a compelling alternative to traditional SRAM and eDRAM - for stateful, in-memory logic. We propose a circuit design that exploits GC-eDRAM's dual-port architecture and nondestructive read operation to perform logic functions directly within the GC-eDRAM memory array. Our simulation results demonstrate a 5us retention time coupled with a 99.5% success rate for computing the logic gates. By incorporating processing-in-memory (PIM) functionality into GC-eDRAM, our approach enhances memory and compute densities, lowers power consumption, and improves overall performance for data-intensive applications.

Problem

• High-density low-power memory for data-intensive applications
• Stateful in-memory logic using GC-eDRAM technology
• Enhancing compute density and reducing data movement overhead

Innovation

• GC-eDRAM for stateful in-memory logic
• Dual-port architecture enables direct logic
• 5us retention with 99.5% success rate