OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits

2025-06-26

AI Summary

To address performance degradation in digital circuits caused by Negative Bias Temperature Instability (NBTI), this paper proposes OptGM—a novel methodology that jointly optimizes gate-level structure and models NBTI sensitivity probabilistically. OptGM identifies critical PMOS nodes based on signal probability thresholds and systematically eliminates them by constructing logic-equivalent composite gates via a graph-traversal-driven gate-merging strategy (driver-driven gate merging). This approach achieves an optimal trade-off among delay, transistor count, and Power-Delay Product (PPC). Experimental validation using HSPICE simulations and ISCAS/ITC benchmark circuits demonstrates that OptGM reduces the number of critical transistors by 89.29% on average, mitigates delay degradation by 23.87%, decreases total transistor count by 6.47%, and improves PPC by 12.8%, with negligible area overhead.

Technology Category

• Machine Learning: Optimization
• Search and Optimization: Sampling/Simulation-based Search
• Constraint Satisfaction and Optimization: Satisfiability

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Security and Privacy: Large-scale security measurements

Abstract

This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes, defined as those with a signal probability exceeding a predefined threshold. Next, based on the proposed optimized algorithm, the sensitizer gate (which drives the critical node) and the sensitive gate (which is fed by it) are merged into a new complex gate. This complex gate preserves the original logic while eliminating NBTI-critical nodes. Finally, to evaluate the effectiveness of OptGM, we assess it on several combinational and sequential benchmark circuits. Simulation results demonstrate that, on average, the number of NBTI-critical transistors (i.e., PMOS transistors connected to critical nodes), NBTI-induced delay degradation, and the total transistor count are reduced by 89.29%, 23.87%, and 6.47%, respectively. Furthermore, OptGM enhances performance per cost (PPC) by 12.8% on average, with minimal area overhead.

Problem

• Mitigate NBTI in digital circuits
• Identify NBTI-critical internal nodes
• Merge gates to reduce NBTI effects

Innovation

• Identifies NBTI-critical nodes effectively
• Merges sensitizer and sensitive gates
• Reduces NBTI impact with minimal overhead