In-Memory Sorting-Searching with Cayley Tree

2025-06-24

AI Summary

To address high CPU utilization and severe memory-access bottlenecks in data-intensive computing, this paper proposes a novel in-memory computing (IMC) architecture based on the Cayley tree. By reconfiguring conventional memory cells into logic-enabled processing nodes, the architecture natively supports in-memory search, extremum (max/min) computation, and sorting—significantly reducing CPU involvement. It achieves O(log n) time complexity for search and extremum operations—distribution-agnostic—and O(n log n) for in-memory sorting. Two FPGA prototypes are implemented: a lightweight version compatible with standard memory interfaces and a fully customized Cayley-tree memory architecture. Experimental results demonstrate that, compared to state-of-the-art IMC designs, our approach delivers both asymptotically lower time complexity and superior energy efficiency for search and sorting workloads.

Technology Category

• Search and Optimization: Distributed Search
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Graph Algorithms and Modeling for the Web: Querying, indexing, and retrieval in Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

This work proposes a computing model to reduce the workload of CPU. It relies on the data intensive computation in memory, where the data reside, and effectively realizes an in-memory computing (IMC) platform. Each memory word, with additional logic, acts as a tiny processing element which forms the node of a Cayley tree. The Cayley tree in turn defines the framework for solving the data intensive computational problems. It finds the solutions for in-memory searching, computing the max (min) in-memory and in-memory sorting while reducing the involvement of CPU. The worst case time complexities of the IMC based solutions for in-memory searching and computing max (min) in-memory are $mathcal{O}log{n}$. Such solutions are independent of the order of elements in the list. The worst case time complexity of in-memory sorting, on the other hand, is $mathcal{O}(nlog{n})$. Two types of hardware implementations of the IMC platform are proposed. One is based on the existing/conventional memory architecture, and the other one is on a newly defined memory architecture. The solutions are further implemented in FPGA platform to prove the effectiveness of the IMC architecture while comparing with the state-of-the art designs.

Problem

• Proposes in-memory computing model to reduce CPU workload
• Solves dataintensive tasks like searching sorting efficiently
• Implements hardware solutions on conventional and new architectures

Innovation

• In-memory computing with Cayley tree nodes
• Hardware implementations on existing and new architectures
• FPGA-proven efficient searching and sorting