HiAER-Spike Software-Hardware Reconfigurable Platform for Event-Driven Neuromorphic Computing at Scale

2026-02-20

AI Summary

This work addresses the challenges of deploying large-scale spiking neural networks (SNNs) on edge and cloud platforms, including low computational efficiency, high memory footprint, and hardware complexity. To this end, the authors propose a modular, software-hardware co-designed, reconfigurable event-driven neuromorphic computing platform capable of real-time execution with up to 160 million neurons and 40 billion synapses. Key innovations include a hierarchical Address Event Representation (HiAER) routing mechanism for efficiently handling sparse connectivity and activity, a memory-efficient storage strategy combined with a parallel event-driven architecture, and a hardware-agnostic Python interface supporting arbitrary network topologies. The platform demonstrates low-latency, energy-efficient inference across multiple benchmarks—including CIFAR-10, DVS gesture recognition, MNIST, and Pong—and has been made publicly accessible to the research community via a web portal.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

In this work, we present HiAER-Spike, a modular, reconfigurable, event-driven neuromorphic computing platform designed to execute large spiking neural networks with up to 160 million neurons and 40 billion synapses - roughly twice the neurons of a mouse brain at faster than real time. This system, assembled at the UC San Diego Supercomputer Center, comprises a co-designed hard- and software stack that is optimized for run-time massively parallel processing and hierarchical address-event routing (HiAER) of spikes while promoting memory-efficient network storage and execution. The architecture efficiently handles both sparse connectivity and sparse activity for robust and low-latency event-driven inference for both edge and cloud computing. A Python programming interface to HiAER-Spike, agnostic to hardware-level detail, shields the user from complexity in the configuration and execution of general spiking neural networks with minimal constraints in topology. The system is made easily available over a web portal for use by the wider community. In the following, we provide an overview of the hard- and software stack, explain the underlying design principles, demonstrate some of the system's capabilities and solicit feedback from the broader neuromorphic community. Examples are shown demonstrating HiAER-Spike's capabilities for event-driven vision on benchmark CIFAR-10, DVS event-based gesture, MNIST, and Pong tasks.

Problem

• neuromorphic computing
• spiking neural networks
• event-driven processing
• scalable architecture
• hardware-software co-design

Innovation

• neuromorphic computing
• spiking neural networks
• hierarchical address-event routing
• reconfigurable platform
• event-driven inference