Locus: A Framework for Exploring and Optimizing Point Addition Hardware for Zero-Knowledge Proofs

2026-09-16

AI Summary

本文提出Locus框架，用于探索和优化零知识证明中的点加硬件设计，通过自动产生ASIC和FPGA实现方案来系统性地研究设计权衡。

Abstract

Zero-Knowledge Proofs (ZKPs) are critical for privacy-preserving and verifiable computation, but their cryptographic primitives impose high computational overheads. One such primitive is point addition (PADD) on elliptic curves. Several prior works have implemented PADDs in hardware, but only for a few specific elliptic curves and design points, leaving a large design space unexplored, and lacking systematic guidance on hardware design trade-offs. To address this gap, we present Locus, a framework dedicated to optimizing and exploring point addition hardware. Given the parameters of any elliptic curve in a supported equation form, Locus automatically generates ASIC and FPGA implementations of PADD, enabling systematic exploration of the PADD design space. Using Locus, we conduct the first comprehensive hardware-focused study of PADD designs, exploring trade-offs over 1,000 design points. On a 12nm technology node, our framework produces PADD designs that yield a $2.71\times$ geomean speedup and $3.11\times$ geomean area reduction compared to prior ASICs, $34.67\times$ geomean speedup over CPU, and $3.15\times$ geomean speedup on end-to-end proof generation when integrated into a prior ZKP accelerator at iso-area. Locus is available at https://github.com/cryptolets/cryptolets/tree/locus.

Problem

• Zero-Knowledge Proofs
• Point Addition
• Elliptic Curves
• Hardware Design
• Optimization

Innovation

• Locus
• point addition
• hardware optimization
• elliptic curves
• Zero-Knowledge Proofs