SpecReuse: Spectral Graph Reuse for Efficient Vision GNN Inference on FPGAs

2026-09-15

AI Summary

为解决FPGA加速视觉图神经网络中的动态图像图构建性能瓶颈问题，提出SpecReuse算法及加速器，通过复用图结构减少延迟和能耗。

Abstract

Dynamic Image Graph Construction (DIGC) is the primary performance bottleneck in FPGA acceleration of Vision Graph Neural Networks (ViGs), reconstructing graph connectivity at every layer through irregular, memory-intensive computation. Existing FPGA accelerators optimize DIGC but still execute it unconditionally, making repeated graph reconstruction a persistent source of latency and energy consumption. We propose the SpecReuse algorithm, which computes compact spectral descriptors of intermediate features and reuses previously constructed graphs when descriptor drift remains below a calibrated threshold. We further present the SpecReuse accelerator, an FPGA architecture that realizes graph reuse through lightweight hardware for spectral descriptor extraction and reuse control while remaining compatible with existing graph-construction accelerators. Experimental results demonstrate up to a $2.69\times$ speedup in end-to-end inference and approximately 58--65\% lower energy per inference with negligible FPGA resource overhead and minimal loss in classification accuracy.

Problem

• Dynamic Image Graph Construction
• FPGA acceleration
• Vision Graph Neural Networks
• performance bottleneck

Innovation

• Spectral Descriptor
• Graph Reuse
• FPGA Accelerator
• Vision GNN