No Scratch Quantum Computing by Reducing Qubit Overhead for Efficient Arithmetics

2025-06-20

AI Summary

Quantum arithmetic circuits suffer from excessive qubit overhead due to reversibility constraints, necessitating numerous ancillary qubits. To address this, we propose the Quantum Hamiltonian Computation (QHC) framework, which encodes input logic directly into the Hamiltonian evolution of a single rotation gate, enabling compact, unitary input-to-output mapping. Leveraging 4×4 Hilbert-space compression encoding and single-gate state encoding, we design reversible half-adders and full-adders requiring only two qubits—significantly reducing resource counts compared to conventional implementations (3→2 qubits and 5-qubit + 5-Fredkin → 2-qubit schemes, respectively). Our approach scales qubit requirements to *O*(log₂*N*) and drastically cuts gate count, achieving the first minimal-resource truth-table-based logic units. This enables low-overhead, reversible arithmetic primitives, offering a viable pathway toward quantum FPGAs and photonic quantum computing architectures.

Technology Category

• Machine Learning: Quantum Machine Learning
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning
• Humans and AI: Other Foundations of Human Computation & AI

Application Category

• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Graph Algorithms and Modeling for the Web: Representation, reconstruction, and subgraph or motif discovery in Web-related graphs

Abstract

Quantum arithmetic computation requires a substantial number of scratch qubits to stay reversible. These operations necessitate qubit and gate resources equivalent to those needed for the larger of the input or output registers due to state encoding. Quantum Hamiltonian Computing (QHC) introduces a novel approach by encoding input for logic operations within a single rotating quantum gate. This innovation reduces the required qubit register $ N $ to the size of the output states $ O $, where $ N = log_2 O $. Leveraging QHC principles, we present reversible half-adder and full-adder circuits that compress the standard Toffoli + CNOT layout [Vedral et al., PRA, 54, 11, (1996)] from three-qubit and four-qubit formats for the Quantum half-adder circuit and five sequential Fredkin gates using five qubits [Moutinho et al., PRX Energy 2, 033002 (2023)] for full-adder circuit; into a two-qubit, 4$ imes $4 Hilbert space. This scheme, presented here, is optimized for classical logic evaluated on quantum hardware, which due to unitary evolution can bypass classical CMOS energy limitations to certain degree. Although we avoid superposition of input and output states in this manuscript, this remains feasible in principle. We see the best application for QHC in finding the minimal qubit and gate resources needed to evaluate any truth table, advancing FPGA capabilities using integrated quantum circuits or photonics.

Problem

• Reducing qubit overhead in quantum arithmetic computations
• Optimizing quantum circuits for classical logic evaluation
• Minimizing qubit and gate resources for truth tables

Innovation

• Encodes input in single rotating quantum gate
• Reduces qubit register to output state size
• Compresses adder circuits into fewer qubits