FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

2021-11-28

International Conference on Electronics, Circuits, and Systems

AI Summary

To address real-time processing challenges posed by high-computational algorithms and high-data-rate payloads in emerging space missions, this work proposes a heterogeneous co-processing architecture tailored for aerospace embedded systems. It pioneers deep integration of a Xilinx Kintex FPGA—responsible for frame synchronization, preprocessing, and hardware acceleration—with an Intel Myriad2 Vision Processing Unit (VPU) dedicated to AI/DSP-intensive computations, interconnected via a low-overhead CIF/LCD parallel interface. The design includes a customized DSP/AI benchmark suite and a joint resource–power optimization strategy. Experimental results demonstrate a VPU AI throughput of 1.2 TOPS (INT8), FPGA resource utilization below 45%, 37% reduction in end-to-end latency, and total system power consumption ≤8.3 W. This work establishes a scalable, low-power, energy-efficient heterogeneous computing paradigm for on-board real-time intelligent processing.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Multi-modal Vision
• Intelligent Robots: Multimodal Perception & Sensor Fusion

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Federated Web and WoT systems, including distributed, federated and edge-based data processing
• Security and Privacy: Security and privacy of machine learning and AI applications
• User Modeling, Personalization and Recommendation: Federated recommendation systems and personalization

Abstract

The advent of computationally demanding algorithms and high data rate instruments in new space applications pushes the space industry to explore disruptive solutions for onboard data processing. We examine heterogeneous computing architectures involving high-performance and low-power commercial SoCs. The current paper implements an FPGA with VPU co-processing architecture utilizing the CIF & LCD interfaces for I/O data transfers. A Kintex FPGA serves as our framing processor and heritage accelerator, while we offload novel DSP/AI functions to a Myriad2 VPU. We prototype our architecture in the lab to evaluate the interfaces, the FPGA resource utilization, the VPU computational throughput, as well as the entire data handling system's performance, via custom benchmarking.

Problem

• Develop FPGA & VPU co-processing for space data handling
• Evaluate performance of heterogeneous computing in space applications
• Test DSP/AI benchmarks on FPGA-VPU architecture

Innovation

• FPGA and VPU co-processing for space
• CIF & LCD interfaces for I/O
• Kintex FPGA with Myriad2 VPU