Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications

2022-10-03

IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip

AI Summary

To address the limitations of conventional processors—insufficient computational capability, radiation susceptibility, and lack of dynamic adaptability—in spaceborne AI/ML applications, this paper proposes a heterogeneous on-board acceleration architecture integrating radiation-hardened (rad-hard) and commercial-off-the-shelf (COTS) FPGAs with an AI-specific instruction-set processor (ASIP). The architecture innovatively combines rad-hard and COTS FPGA resources and incorporates custom compute units inspired by vision processing units (VPUs) and tensor processing units (TPUs), enabling deployment of high-order AI models and in-orbit dynamic reconfiguration. Through radiation-hardened design, a reconfigurable computing framework, and industrial-grade benchmarking, multi-platform prototype validation is achieved. Compared to representative spaceborne processors, the architecture delivers over 10× improvement in energy efficiency, enables real-time on-board image recognition and autonomous mission decision-making, and establishes a scalable architectural paradigm for high-reliability, high-performance spaceborne intelligent computing.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Computer Vision: Remote Sensing / Geospatial AI

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Security and Privacy: Security and privacy of machine learning and AI applications
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

The success of AI/ML in terrestrial applications and the commercialization of space are now paving the way for the advent of AI/ML in satellites. However, the limited processing power of classical onboard processors drives the community towards extending the use of FPGAs in space with both rad-hard and Commercial-Off-The-Shelf devices. The increased performance of FPGAs can be complemented with VPU or TPU ASIP coprocessors to further facilitate high-level AI development and inflight reconfiguration. Thus, selecting the most suitable devices and designing the most efficient avionics architecture becomes crucial for the success of novel space missions. The current work presents industrial trends, comparative studies with inhouse benchmarking, as well as architectural designs utilizing FPGAs and AI accelerators towards enabling AI/ML in future space missions.

Problem

• Enabling AI/ML in satellites with limited onboard processing power
• Extending FPGA use in space with rad-hard and COTS devices
• Designing efficient avionics architecture for AI/ML in space missions

Innovation

• FPGA acceleration for space AI/ML
• ASIP co-processors enhance performance
• In-flight reconfiguration with VPU/TPU