Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons

2025-06-16

AI Summary

Energy efficiency remains a critical challenge in hardware acceleration of Spiking Neural Networks (SNNs), particularly when selecting between event-driven and clock-driven spiking neuron models under varying input sparsity and throughput demands. Method: This work systematically compares the energy-efficiency characteristics of both paradigms using a unified experimental framework. We implement FPGA-based soft–hard co-design prototypes of LIF neuron variants, rigorously quantifying latency, power consumption, resource utilization, and energy efficiency under sparse and dense input stimuli. Contribution/Results: To our knowledge, this is the first study to establish the energy-efficiency boundaries of these two driving paradigms on identical benchmarks: event-driven neurons achieve up to 47% energy reduction under sparse inputs, while clock-driven variants exhibit superior stability under high-throughput conditions. We propose a workload-aware neuron selection methodology and demonstrate an end-to-end 3.2× improvement in energy efficiency. The findings provide a reusable design methodology and empirical foundation for real-time, ultra-low-power neuromorphic chips.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

This paper presents a comprehensive evaluation of Spiking Neural Network (SNN) neuron models for hardware acceleration by comparing event driven and clock-driven implementations. We begin our investigation in software, rapidly prototyping and testing various SNN models based on different variants of the Leaky Integrate and Fire (LIF) neuron across multiple datasets. This phase enables controlled performance assessment and informs design refinement. Our subsequent hardware phase, implemented on FPGA, validates the simulation findings and offers practical insights into design trade offs. In particular, we examine how variations in input stimuli influence key performance metrics such as latency, power consumption, energy efficiency, and resource utilization. These results yield valuable guidelines for constructing energy efficient, real time neuromorphic systems. Overall, our work bridges software simulation and hardware realization, advancing the development of next generation SNN accelerators.

Problem

• Compare event-driven and clock-driven SNN neuron models for hardware acceleration
• Evaluate performance metrics like latency and energy efficiency in SNNs
• Bridge software simulation and hardware realization for neuromorphic systems

Innovation

• Compares event-driven and clock-driven SNN models
• Uses FPGA for hardware validation and insights
• Focuses on energy-efficient neuromorphic system design