Mapping and Scheduling Spiking Neural Networks On Segmented Ladder Bus Architectures

2025-06-12

AI Summary

Existing dynamic segmented bus architectures for large-scale neuromorphic chips suffer from inefficient and non-scalable control planes, failing to address the sparsity, asynchrony, and locality inherent in spike-based communication—resulting in high control overhead and constrained area efficiency and energy efficiency. This paper proposes the first context-aware, lightweight control-plane design methodology tailored for segmented trapezoidal buses. Our approach integrates event-driven scheduling, dynamic bus segmentation, and sparse communication modeling to co-optimize control logic with neural activity characteristics. FPGA implementation and simulation validation demonstrate that the proposed control plane reduces area by over an order of magnitude relative to the data plane, enables linear scalability with network size, significantly lowers control overhead, and achieves superior energy efficiency and area utilization compared to conventional bus control schemes.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Machine Learning: Hardware-aware ML

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Security and Privacy: Large-scale security measurements

Abstract

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. The communication patterns in these systems are inherently sparse, asynchronous, and localized, as neural activity is characterized by temporal sparsity with occasional bursts of high traffic. These characteristics require optimized interconnects to handle high-activity bursts while consuming minimal power during idle periods. Among the proposed interconnect solutions, the dynamic segmented bus has gained attention due to its structural simplicity, scalability, and energy efficiency. Since the benefits of a dynamic segmented bus stem from its simplicity, it is essential to develop a streamlined control plane that can scale efficiently with the network. In this paper, we present a design methodology for a scenario-aware control plane tailored to a segmented ladder bus, with the aim of minimizing control overhead and optimizing energy and area utilization. We evaluated our approach using a combination of FPGA implementation and software simulation to assess scalability. The results demonstrated that our design process effectively reduces the control plane's area footprint compared to the data plane while maintaining scalability with network size.

Problem

• Optimizing interconnect for sparse neural spike communication
• Designing scalable control plane for segmented bus architecture
• Reducing control overhead while maintaining energy efficiency

Innovation

• Dynamic segmented bus for energy-efficient spike communication
• Scenario-aware control plane minimizing overhead and area
• FPGA and software simulation for scalable evaluation