Design of a 6-bit Threshold Inverter Quantization (TIQ) Flash Analog to Digital Converter (ADC)

2025-01-08

AI Summary

Conventional flash ADCs suffer from process/temperature sensitivity and excessive area/power overhead due to resistor-divider networks and op-amp-based comparators. To address these limitations, this paper proposes a 6-bit fully digital flash ADC based on Threshold-Inversion Quantization (TIQ). The design replaces the conventional resistor ladder and op-amp comparators entirely with a TIQ comparator array built from two-stage CMOS inverters. A gain-enhancement circuit is integrated to improve resolution, while a 1-out-of-n encoder combined with a fat-tree architecture—novelly introduced for 6-bit flash ADCs—is employed to minimize encoding delay and area. Post-layout Tanner simulations in 0.25-μm CMOS demonstrate robust performance: at 2.5 V supply, power consumption is 6.25 mW with 1.07 μs latency for 10 kHz input; for 10 MHz input, it consumes 12.12 mW with 947.14 ns latency. The results validate the ADC’s high speed, low power, and strong process robustness.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Search and Optimization: Learning to Search

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Abstract

An ADC is used to convert analog signals into binary signals. Compared with many other types of ADCs, flash converters are incredibly quick. A typical Flash ADC consists of 2n resistors, 2n-1 op-amp comparators, and an encoder which requires more area. The resistors and comparators can be eliminated by using threshold inverter quantization (TIQ) comparators. As a voltage comparator, TIQ technique uses two cascaded CMOS inverters. So that there will be no variation in the fabrication process, and temperature. A 6-bit flash ADC based on threshold inverter quantization (TIQ) comparator was designed and software implementation was performed employing a fat tree encoder with 0.25 micrometer CMOS technology. The design consists of 2n-1 TIQ comparator arrays, a gain booster, a 1-out-of-n code generator, and a fat tree encoder. This TIQ flash ADC is simulated with the Tanner EDA Tool. Here the supply voltage is 2.5 V, input frequency of 10 kHz and 10 MHz. The power consumption of the ADC is 6.25 mW, and the propagation delay is 1.07 microseconds for 10 kHz input frequency. For 10 MHz input frequency, power consumption is 12.12 mW and propagation delay is 947.14 ms.

Problem

• Analog-to-Digital Conversion
• Threshold Inversion Quantization
• Flash ADC Design

Innovation

• Threshold Inversion Quantization (TIQ)
• 6-bit Flash ADC
• Robustness to Process and Temperature Variation