🤖 AI Summary
This paper addresses the problem of *global consistency verification*—i.e., deciding whether all possible executions of a register machine satisfy the semantic constraints—of the release-acquire (RA) memory model and its strong/weak variants (SRA/WRA). It provides the first systematic formal solution to this verification problem, establishing tight computational complexity characterizations: WRA verification is solvable in O(n⁵), whereas RA and SRA verification are both NP- and coNP-hard with a PSPACE upper bound. The method integrates register-machine modeling, semantic encoding of memory models, and rigorous computational complexity analysis. Key contributions are: (1) the first precise complexity classification for global verification of RA-class semantics; (2) a theoretical delineation of the expressive limits of register machines for modeling concurrent semantics; and (3) a decidability foundation and algorithmic basis for reliability verification of memory-model implementations.
📝 Abstract
The Release-Acquire (RA) semantics and its variants are some of the most fundamental models of concurrent semantics for architectures, programming languages, and distributed systems. Several steps have been taken in the direction of testing such semantics, where one is interested in whether a single program execution is consistent with a memory model. The more general verification problem, i.e., checking whether all allowed program runs are consistent with a memory model, has still not been studied as much. The purpose of this work is to bridge this gap. We tackle the verification problem, where, given an implementation described as a register machine, we check if any of its runs violates the RA semantics or its Strong (SRA) and Weak (WRA) variants. We show that verifying WRA in this setup is in O([)n5 ], while verifying the RA and SRA is in both NP- and coNP-hard, and provide a PSPACE upper bound. This both answers some fundamental questions about the complexity of these problems, but also provides insights on the expressive power of register machines as a model.