PoSyn: Secure Power Side-Channel Aware Synthesis

2025-06-09

AI Summary

Cryptographic hardware is vulnerable to power side-channel (PSC) attacks during logic synthesis, while conventional masking countermeasures suffer from high integration complexity, significant area overhead, and susceptibility to synthesis-driven optimizations that compromise security. Method: This paper proposes the first leakage-aware logic synthesis framework deeply embedded in the RTL-to-netlist flow. It introduces a novel standard-cell mapping optimization based on mutual information minimization, formulates a technology-library-aware leakage cost function, and integrates RTL-level vulnerability modeling with secure-constrained optimal bipartite matching. A theoretical proof guarantees strict minimization of power leakage. Results: Evaluated on AES, RSA, PRESENT, Saber, and Kyber, the framework reduces DPA and CPA attack success rates to 3% and 6%, respectively; TVLA shows no statistically significant leakage; and area overhead is only 26.4% of that incurred by traditional masking schemes.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Constraint Satisfaction and Optimization: Satisfiability

Application Category

• Security and Privacy: Applications of cryptography
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Measurement, analysis, and circumvention of Web censorship

Abstract

Power Side-Channel (PSC) attacks exploit power consumption patterns to extract sensitive information, posing risks to cryptographic operations crucial for secure systems. Traditional countermeasures, such as masking, face challenges including complex integration during synthesis, substantial area overhead, and susceptibility to optimization removal during logic synthesis. To address these issues, we introduce PoSyn, a novel logic synthesis framework designed to enhance cryptographic hardware resistance against PSC attacks. Our method centers on optimal bipartite mapping of vulnerable RTL components to standard cells from the technology library, aiming to minimize PSC leakage. By utilizing a cost function integrating critical characteristics from both the RTL design and the standard cell library, we strategically modify mapping criteria during RTL-to-netlist conversion without altering design functionality. Furthermore, we theoretically establish that PoSyn minimizes mutual information leakage, strengthening its security against PSC vulnerabilities. We evaluate PoSyn across various cryptographic hardware implementations, including AES, RSA, PRESENT, and post-quantum cryptographic algorithms such as Saber and CRYSTALS-Kyber, at technology nodes of 65nm, 45nm, and 15nm. Experimental results demonstrate a substantial reduction in success rates for Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) attacks, achieving lows of 3% and 6%, respectively. TVLA analysis further confirms that synthesized netlists exhibit negligible leakage. Additionally, compared to conventional countermeasures like masking and shuffling, PoSyn significantly lowers attack success rates, achieving reductions of up to 72%, while simultaneously enhancing area efficiency by as much as 3.79 times.

Problem

• Enhancing cryptographic hardware resistance against Power Side-Channel attacks
• Minimizing PSC leakage via optimal RTL-to-netlist component mapping
• Reducing attack success rates and improving area efficiency

Innovation

• Optimal bipartite mapping minimizes PSC leakage
• Cost function integrates RTL and cell characteristics
• Modifies mapping criteria without altering functionality