ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors

2025-06-07

AI Summary

Standard Bayesian optimization (BO) struggles with categorical parameter constraints (e.g., branch predictor type) and suffers from exponentially increasing evaluation costs as FPGA soft-processor designs grow in complexity. To address these challenges, this paper proposes a constraint-aware, customized BO framework. Its key contributions are: (1) a disjunctive-logic-based constraint modeling method to rigorously encode categorical dependencies; (2) a classification-aware covariance kernel that explicitly captures semantic relationships among categorical parameters; and (3) an acquisition function incorporating synthetic checkpoint reuse and evaluation-time-aware penalization. Evaluated on RocketChip, BOOM, and EL2 VeeR FPGA platforms using seven RISC-V benchmarks (including *multiply*), the framework reduces BOOM’s execution time by 35% on *multiply* and shortens the design cycle by 74% compared to Boomerang.

Technology Category

• Constraint Satisfaction and Optimization: Constraint Optimization
• Search and Optimization: Mixed Discrete/Continuous Search
• Machine Learning: Hardware-aware ML

Application Category

• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• User Modeling, Personalization and Recommendation: Fairness-aware retrieval and ranking
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Bayesian Optimization (BO) has shown promise in tuning processor design parameters. However, standard BO does not support constraints involving categorical parameters such as types of branch predictors and division circuits. In addition, optimization time of BO grows with processor complexity, which becomes increasingly significant especially for FPGA-based soft processors. This paper introduces ASPO, an approach that leverages disjunctive form to enable BO to handle constraints involving categorical parameters. Unlike existing methods that directly apply standard BO, the proposed ASPO method, for the first time, customizes the mathematical mechanism of BO to address challenges faced by soft-processor designs on FPGAs. Specifically, ASPO supports categorical parameters using a novel customized BO covariance kernel. It also accelerates the design evaluation procedure by penalizing the BO acquisition function with potential evaluation time and by reusing FPGA synthesis checkpoints from previously evaluated configurations. ASPO targets three soft processors: RocketChip, BOOM, and EL2 VeeR. The approach is evaluated based on seven RISC-V benchmarks. Results show that ASPO can reduce execution time for the ``multiply'' benchmark on the BOOM processor by up to 35% compared to the default configuration. Furthermore, it reduces design time for the BOOM processor by up to 74% compared to Boomerang, a state-of-the-art hardware-oriented BO approach.

Problem

• Handles constraints with categorical parameters in BO
• Reduces optimization time for FPGA soft processors
• Improves execution and design time for RISC-V benchmarks

Innovation

• Customized BO kernel for categorical parameters
• Accelerates design via time-penalized acquisition function
• Reuses FPGA synthesis checkpoints for efficiency