VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

2025-06-08

AI Summary

Early-stage chip design requires precise, line-level prediction of timing violations and routing congestion risks from Verilog code. Method: This paper proposes the first end-to-end line-level quality prediction method that operates directly on raw Verilog source code—without manual graph construction or handcrafted feature engineering. It leverages a specialized code large language model to jointly extract local (line-level) and global (module-level) embeddings, which are fused to enable dual-granularity (line- and module-level) quality inference. Contribution/Results: Our approach achieves the first fine-grained, quantitative risk assessment for individual Verilog lines. Experiments show F1 scores of 0.86–0.95 for line-level congestion and timing prediction, with a mean absolute percentage error of only 4%—outperforming state-of-the-art methods by 10–14 percentage points. This significantly enhances both accuracy and efficiency in front-end design quality evaluation.

Technology Category

• Planning, Routing, and Scheduling: Planning with Language Models
• Machine Learning: Calibration & Uncertainty Quantification
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language

Application Category

• Economics, Online Markets and Human Computation: LLM based quality controls for crowd work
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a commonly used programming language for hardware design). It is especially important yet complex to predict individual lines of code that cause timing violations or downstream routing congestion. Prior works have tried approaches like converting Verilog into an intermediate graph representation and using LLM embeddings alongside other features to predict module-level quality, but did not consider line-level quality prediction. We propose VeriLoC, the first method that predicts design quality directly from Verilog at both the line- and module-level. To this end, VeriLoC leverages recent Verilog code-generation LLMs to extract local line-level and module-level embeddings, and train downstream classifiers/regressors on concatenations of these embeddings. VeriLoC achieves high F1-scores of 0.86-0.95 for line-level congestion and timing prediction, and reduces the mean average percentage error from 14% - 18% for SOTA methods down to only 4%. We believe that VeriLoC embeddings and insights from our work will also be of value for other predictive and optimization tasks for complex hardware design.

Problem

• Predicts hardware design quality from Verilog code
• Identifies problematic lines causing timing violations
• Improves accuracy of congestion and timing predictions

Innovation

• Uses Verilog code-generation LLMs for embeddings
• Combines line-level and module-level embeddings
• Trains classifiers for precise quality prediction