Image Synthesis Using Spintronic Deep Convolutional Generative Adversarial Network

2026-01-04

AI Summary

This work addresses the inefficiency of conventional von Neumann architectures in meeting the high computational and energy demands of generative adversarial networks (GANs). The authors propose a hybrid CMOS–spintronic deep convolutional GAN (DCGAN) architecture that integrates, for the first time, a 6-bit synapse crossbar array based on magnetic skyrmions with domain-wall-tuned tunable Leaky ReLU units. The generator is restructured using zero-padded convolutions to align with hardware constraints. Combined with a parallel MTJ readout mechanism, this design significantly enhances energy efficiency and hardware compatibility. Evaluated on the Fashion MNIST and Anime Face datasets, the system achieves FID scores of 27.5 and 45.4, respectively, with per-image inference energy consumption as low as 4.9 nJ and 24.72 nJ, and training energy costs of only 14.97 nJ and 74.7 nJ.

Technology Category

• Computer Vision: Generative Adversarial Networks (GANs) for Vision
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications
• Social Networks and Social Media: Generative AI / large language models and their impact on social systems
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

The computational requirements of generative adversarial networks (GANs) exceed the limit of conventional Von Neumann architectures, necessitating energy efficient alternatives such as neuromorphic spintronics. This work presents a hybrid CMOS-spintronic deep convolutional generative adversarial network (DCGAN) architecture for synthetic image generation. The proposed generative vision model approach follows the standard framework, leveraging generator and discriminators adversarial training with our designed spintronics hardware for deconvolution, convolution, and activation layers of the DCGAN architecture. To enable hardware aware spintronic implementation, the generator's deconvolution layers are restructured as zero padded convolution, allowing seamless integration with a 6-bit skyrmion based synapse in a crossbar, without compromising training performance. Nonlinear activation functions are implemented using a hybrid CMOS domain wall based Rectified linear unit (ReLU) and Leaky ReLU units. Our proposed tunable Leaky ReLU employs domain wall position coded, continuous resistance states and a piecewise uniaxial parabolic anisotropy profile with a parallel MTJ readout, exhibiting energy consumption of 0.192 pJ. Our spintronic DCGAN model demonstrates adaptability across both grayscale and colored datasets, achieving Fr'echet Inception Distances (FID) of 27.5 for the Fashion MNIST and 45.4 for Anime Face datasets, with testing energy (training energy) of 4.9 nJ (14.97~nJ/image) and 24.72 nJ (74.7 nJ/image).

Problem

• Generative Adversarial Networks
• Image Synthesis
• Energy Efficiency
• Von Neumann Architecture
• Neuromorphic Computing

Innovation

• spintronic DCGAN
• skyrmion synapse
• domain wall ReLU
• neuromorphic hardware
• energy-efficient GAN