🤖 AI Summary
To address the trade-off between accuracy and speed in high-speed optical packet header recognition, this paper proposes an all-optical reservoir computing architecture based on integrated double-ring resonators (DRRs). It achieves, for the first time, configuration-agnostic global optimization of the delay–bandwidth product (DBP) by employing deep reinforcement learning—specifically the Proximal Policy Optimization (PPO) algorithm—to rapidly optimize the entire DRR parameter space, thereby unifying support for cascaded, parallel, and embedded configurations. The designed device features an ultra-compact chip footprint and a “flat-top” delay spectrum. Experimental evaluation demonstrates word error rates (WERs) of 5×10⁻⁴ and 9×10⁻⁴ on 3-bit and 6-bit header recognition tasks, respectively—improving upon prior work by one order of magnitude. These results validate the efficacy and advancement of the proposed approach for high-speed, high-accuracy all-optical signal processing.
📝 Abstract
Optical packet header recognition is an important signal processing task of optical communication networks. In this work, we propose an all-optical reservoir, consisting of integrated double-ring resonators (DRRs) as nodes, for fast and accurate optical packet header recognition. As the delay-bandwidth product (DBP) of the node is a key figure-of-merit in the reservoir, we adopt a deep reinforcement learning algorithm to maximize the DBPs for various types of DRRs, which has the advantage of full parameter space optimization and fast convergence speed. Intriguingly, the optimized DBPs of the DRRs in cascaded, parallel, and embedded configurations reach the same maximum value, which is believed to be the global maximum. Finally, 3-bit and 6-bit packet header recognition tasks are performed with the all-optical reservoir consisting of the optimized cascaded rings, which have greatly reduced chip size and the desired “flat-top” delay spectra. Using this optical computing scheme, word-error rates as low as 5×10-4 and 9×10-4 are achieved for 3-bit and 6-bit packet header recognition tasks, respectively, which are one order of magnitude better than the previously reported values.
