🤖 AI Summary
To address the limited precision and dynamic range of IEEE 754 floating-point arithmetic, this paper proposes and implements a dedicated hardware codec for the Takum number system—a generalized logarithmic number system (LNS). Methodologically, we introduce a novel exponent encoding scheme and a hybrid LNS/linear internal representation, enabling seamless bidirectional conversion between native Takum format and linear Takum (a floating-point–like variant). The design is modeled in VHDL and realized on FPGA using a scalable architecture. Compared to state-of-the-art posit codecs, our implementation achieves up to 38% lower encoding/decoding latency and reduces LUT utilization by 50%, while preserving bounded ultra-wide dynamic range (>10⁶⁰⁰⁰). This significantly improves both accuracy and efficiency for extreme-magnitude computations, offering a hardware-efficient pathway for high-dynamic-range numerical computing.
📝 Abstract
The takum machine number format has been recently proposed as an enhancement over the posit number format, which is considered a promising alternative to the IEEE 754 floating-point standard. Takums retain the useful posit properties, but feature a novel exponent coding scheme that yields more precision for small and large magnitude numbers and a much higher and bounded dynamic range. This paper presents the design and implementation of a hardware codec for both takums (logarithmic number system, LNS) and linear takums (floating-point format). The codec design is emphasised, as it constitutes the primary distinguishing feature compared to logarithmic posits (LNS) and posits (floating-point format), which otherwise share similar internal representations. Furthermore, a novel internal representation for LNS is proposed. The proposed takum codec, implemented in VHDL, demonstrates near-optimal scalability and performance on an FPGA. It achieves latency reductions of up to 38% and reduces LUT utilisation up to 50% compared to state-of-the-art posit codecs.