LLM4RTL: Tool-Assisted LLM for RTL Generation

2026-06-13

AI Summary

This work addresses the limitations of open-source Verilog/RTL code generation, which stem from the scarcity of high-quality training data and the insufficient logical reasoning and rule-expression capabilities of large language models (LLMs). To overcome these challenges, the authors propose the JRCRC pipeline, introducing a novel “Judge–Refine–Check” iterative mechanism. This approach integrates hierarchical LLMs, low-rank fine-tuning, rule-based preprocessing tools, and a dynamic logical inference module to automatically derive logical relationships from tabular data and construct a high-quality RTL training dataset. Evaluated on the VerilogEval benchmark, the method significantly outperforms existing techniques, achieving performance comparable to GPT-4o with a substantially smaller model size, thereby effectively mitigating the reasoning deficiencies of LLMs in hardware logic generation.

Abstract

Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems. Concurrently, a significant body of research has developed which explores a growing variety of methods and systems for applying LLMs to hardware and chip design (e.g., systems for RTL code generation based on functional description). However, when it comes to open Verilog/RTL code-generation, we need high-quality training samples to build specialized and more effective LLM systems through fine-tuning or low-rank adaptation. Here, we propose a ``judge-renew-check-renew-check'' (JRCRC) pipeline which updates a current public dataset using a hierarchy of state-of-the-art commercial LLM models differing in their costs and capabilities in RTL code generation. This approach achieves a cost-effective mechanism for filtering and refining code-generation samples into a higher-quality training dataset. Our experiments also identify some common weaknesses of LLMs in rule-based reasoning and logic, and consequently, in RTL code-generation. Having identified these weaknesses, we develop an architecture for incorporating pre-processing tools to dynamically assist the LLMs in inferring logical relationships from tabular data formats. With our tools-assisted architecture for RTL code generation, we achieve significant overall performance gains in the VerilogEval benchmark and outperform many state-of-the-art methods. Our LLM4RTL system achieves performance comparable to that of GPT-4O using a significantly much smaller LLM.

Problem

• RTL generation
• LLM
• code generation
• hardware design
• Verilog

Innovation

• LLM4RTL
• RTL generation
• tool-assisted LLM
• JRCRC pipeline
• VerilogEval