CREST: Deployment-Realistic Hardware-in-the-Loop NAS for Embedded Sensing Systems

2026-06-12

AI Summary

This work addresses the limitations of existing approaches for deploying neural networks on low-power microcontrollers, which rely on static proxy metrics like FLOPs or oversimplified assumptions that fail to capture real-world energy consumption, memory usage, and scheduling constraints, often leading to suboptimal model selection. To overcome this, the authors propose CREST, a novel framework that introduces hardware-in-the-loop evaluation into neural architecture search for microcontroller units (MCUs). CREST enables joint optimization of model architecture, target hardware platform, scheduling policy, and deployment configuration through a configurable workflow. It supports quantization-aware search, cross-platform backends, reproducible search trajectories, and scoring based on actual measured energy and scheduling behavior. Evaluated on an inertial odometry task, CREST reduces real-world energy consumption by over 40% compared to models selected via conventional proxy metrics, while also revealing significant shifts in the Pareto frontier under continuous inference with duty-cycled scheduling and highlighting cross-board deployment overheads.

Abstract

Deploying neural networks on low-power microcontrollers (MCUs) requires selecting model architectures under tight memory, latency, and energy constraints. Existing workflows often simplify this process along one or more axes: static proxy costs such as FLOPs or parameters, treating one MCU as representative, and continuous-inference tests instead of deployed sensing schedules. These assumptions can mis-rank Pareto-front candidates, miss infeasible deployments, and obscure schedule-dependent energy. We present CREST (Cross-platform Runtime Evaluation and Search Tool), a deployment-realistic hardware-in-the-loop (HIL) neural architecture search (NAS) framework for MCU sensing systems. CREST keeps the optimizer, HIL measurement boundary, logging, and replay workflow fixed while exposing workload, model family, target backend, schedule, quantization, and scoring policy as configurable axes. This makes deployment effects experimentally separable within one reusable workflow. We evaluate CREST on inertial odometry and audio classification across three Arm Cortex-M targets. For inertial odometry, measured-energy HIL search reduces median per-inference energy by 41.7% versus FLOPs-based selection and 40.8% versus memory-traffic-based selection at similar error. FLOPs-based selection also chooses infeasible deployments on memory-constrained targets. On the STM32 N657 target, continuous-inference and duty-cycled searches produce different Pareto frontiers. For audio classification, the same application-level policy selects different DS-CNN architectures on different boards, and cross-board replay changes deployment cost substantially. Overall, CREST shows that deployment-realistic MCU NAS must jointly optimize model architecture, target platform, runtime schedule, and deployment policy rather than relying only on static proxy costs or continuous-inference measurements.

Problem

• neural architecture search
• hardware-in-the-loop
• embedded sensing systems
• deployment constraints
• microcontroller

Innovation

• hardware-in-the-loop
• neural architecture search
• deployment-realistic
• microcontroller
• energy-aware optimization