Unicorn-CIM: Unconvering the Vulnerability and Improving the Resilience of High-Precision Compute-in-Memory

📅 2025-06-02
📈 Citations: 0
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🤖 AI Summary
High-precision floating-point compute-in-memory (FP-CIM) suffers from poor soft-error resilience, particularly due to catastrophic accuracy degradation caused by exponent-bit errors in DNN inference. Method: We propose an algorithm-hardware co-design approach: (i) an exponent-aware model fine-tuning algorithm to optimize exponent distribution, and (ii) a lightweight, exponent-specific ECC encoding scheme. Results: Evaluated on an SRAM-based FP-CIM architecture, our method incurs only 8.98% additional logic overhead while providing robust soft-error protection—achieving near-lossless high-precision DNN inference accuracy (drop <0.1%). This work is the first to identify and characterize the intrinsic vulnerability of exponent bits in FP-CIM, overcoming the granularity mismatch between conventional ECCs and floating-point data representations. It establishes a scalable fault-tolerance paradigm for FP-CIM, enabling reliable edge training and high-integrity inference.

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📝 Abstract
Compute-in-memory (CIM) architecture has been widely explored to address the von Neumann bottleneck in accelerating deep neural networks (DNNs). However, its reliability remains largely understudied, particularly in the emerging domain of floating-point (FP) CIM, which is crucial for speeding up high-precision inference and on device training. This paper introduces Unicorn-CIM, a framework to uncover the vulnerability and improve the resilience of high-precision CIM, built on static random-access memory (SRAM)-based FP CIM architecture. Through the development of fault injection and extensive characterizations across multiple DNNs, Unicorn-CIM reveals how soft errors manifest in FP operations and impact overall model performance. Specifically, we find that high-precision DNNs are extremely sensitive to errors in the exponent part of FP numbers. Building on this insight, Unicorn-CIM develops an efficient algorithm-hardware co-design method that optimizes model exponent distribution through fine-tuning and incorporates a lightweight Error Correcting Code (ECC) scheme to safeguard high-precision DNNs on FP CIM. Comprehensive experiments show that our approach introduces just an 8.98% minimal logic overhead on the exponent processing path while providing robust error protection and maintaining model accuracy. This work paves the way for developing more reliable and efficient CIM hardware.
Problem

Research questions and friction points this paper is trying to address.

Identifying vulnerabilities in floating-point Compute-in-Memory (CIM) architectures
Improving resilience of high-precision DNNs against soft errors
Co-designing hardware and algorithms for efficient error protection in CIM
Innovation

Methods, ideas, or system contributions that make the work stand out.

SRAM-based FP CIM architecture
Fault injection and DNN characterization
Algorithm-hardware co-design with ECC
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